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Add captio A global FPGA design contest held by Intel and Terasic, starting tomorrow! All FPGA developers can join the contest as teams and compete or join as a community member and vote! "The Innovate Asia, Nordic, and North America contests have inspired thousands of aspiring engineers to design, create, and innovate. This year, these regional events have been combined into a single global contest – Innovate FPGA – where teams from around the world compete as they invent the future of embedded compute with Terasic and Intel. The competition is open to everyone including students, professors, makers, and industry. Teams can showcase their creativity and innovation with actual results and real-world designs. Eligible teams will receive a FREE DE10-Nano development kit!"

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Men marry women wishing they will never change, but they do. Women marry men wishing they will be able to change them, but they don't. When I was young, even during my University studies, I was a real disaster in anything related to order and tidiness. My room was always a mess. Whenever my mother or any other would try to change my ways (even a little bit), I would say what many like me love to say: - "In the disorder, I know where everything is. When my mother makes some order, I can't find anything". And to demonstrate that the half-joke at the beginning of this article is not true, I must say that I changed a lot since I married. My home won't appear in a decoration magazine, but it is not close at all to my young-days' complete-mess room. The other reason I have to train me all the time to be a more tidy person is that I work in FPGA design. So if you are rolling your eyes thinking that order has nothing to do with design, and I'd better publi...

In the  first article of this series , we defined what an HW arbiter is. In this entry of the tutorial, we will see a simple implementation of a VHDL arbiter. The arbiter of this example has three request inputs and three grant outputs. It has a fixed priority for the masters. The lower the master number, the higher its priority. The block also has a  busy  signal. Arbitration of the bus is done only while it is inactive. If the bus has already been granted to an agent, even if a bigger priority master requests the bus, the current transaction must complete before the arbiter grants the bus to another master. Continue reading…

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Many times I find myself in the need of generating data for testing. We need data for verification, either done on simulation or on the real target. One easy way to test our system is to generate data vectors on RAM. Altera RAM IP includes the ability to initialize RAM contents during power-up by means of a .hex file. One problem of the .hex file format is that it is quite unreadable for humans. Altera came to our rescue with the .mif format, which is text based and very easy to understand. The application I present below initializes a memory (generating an .hex file). The size and width of the memory are parameters. The Matlab application generates both a init_mem.mif and a init_mem.hex file. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 %------------------------------------------- % Generate Parameters ram_size = 256 ; % In words word_size = 16...

What is an arbiter? What is an arbiter? An arbiter is a very common block used on HW designs. I think I can find the best example of an arbiter at home. When my two kids were teenagers, I had only one car. On Friday and Saturday evenings, there was usually a conflict over who got to use the car. Usually, it was on me to decide (arbiter) who got the car. Not an easy task. (I still have only one car. It just happens that my kids are not teenagers anymore, and praise the Lord, they have their own cars). Continue reading...  

The concept of machine learning is not new. Attempts at systems emulating intelligent behavior, like expert systems, go as far back as the early 1980's. And the very notion of modern Artificial Intelligence has a long history. The name itself was coined at a Dartmouth College conference (1956), but the idea of an "electronic brain" was born together with the development of modern computers. AI as an idea accompanies us from the dawn of human history. Three latest development are pushing forward "Machine Learning": Powerful distributed processors Cheap and high volume storage High bandwidth interconnection to bring the data to the processors As in many other fields, development of Machine Learning is also seeing development on algorithms that take advantage of the new hardware capabilities. There are four types of algorithms used in machine learning: Supervised - The vast majority of systems today. These systems are 'trained' based on past d...

Guinness is a GUI based framework that includes both a training on a GPU, and a bitstream generation for an FPGA using the Xilinx SDSoC. This tool uses the Chainer deep learning framework to train a binarized CNN. Also, it uses optimization techniques for an FPGA implementation. Compared with the conventional FPGA realizations, although the classification accuracy is 6.5% decayed, the performance is 2.45 times faster, the power efficiency is slightly better, and the area efficiency is 2.68 times better. Compared with the ARM Cortex-A57, it is 136.8 times faster, it dissipates 3.1 times much power, and its performance per power efficiency is 44.7 times better. Also, compared with the Maxwell embedded GPU, it is 4.9 times faster, it dissipates 1.3 times much power, and its performance per power efficiency is 3.8 times better.  Details are shown in following papers: [Nakahara IPDPSW2017] H. Yonekawa and H. Nakahara, "On-Chip Memory Based Binarized Convolutional Dee...

FPGAs and GPUs: a Tour of SETI's Computer Hardware David MacMahon is a research astronomer with Berkeley SETI Research Center. Dave works on several projects at BSRC, including Breakthrough Listen, designing many of the computer systems we use to process data collected from our telescopes. If you've ever been curious what hardware is required to search for ET, check out this tour of Berkeley SETI behind the scenes.

Image Source: Linked In Machine Learning is a hot I+D topic. One of the strategies used in Machine Learning is to learn by means of neural networks. You can get a free introduction to neural networks here . I also warmly recommend Andrew Ng's introductory course to Machine Learning on Coursera . Machine Learning neural networks were inspired by biological neural networks, and are easily applied but highly effective in image processing algorithms, like handwritten text recognition. More complex neural networks algorithms are being implemented on what is called Deep Machine Learning, using neural networks with many layers of complexity. Typically a neural network is trained, or it learns, from its exposure to thousands of 'good' and 'bad' examples of the image to be recognized or classfied. For example, a neural network that has to recognize handwritten numbers, will be exposed to thousands of examples of numbers written by different people, and even with...

Reusable blocks (Image source: Altium) This whitepaper  by Charles Fulk and RC Cofer is an excellent summary of several techniques, tools and design guidelines for FPGA: FPGA design process Revision control Coding guidelines Scripting automation PCB design for FPGA VHDL capture and simulation (including OS-VVM package) Project Management Design Resources The whitepaper is available here

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Hi, In this series of articles, I am going to present the design of an AXI4-Stream master. As I often do in my tutorials, I will try to show the design procedure for the block, starting from a “bare bones” solution and gradually adding features to it. Xilinx provides a wide range of AXI peripherals/IPs from which to choose. My purpose in making my own block was to learn the protocol ‘hands-on’. As a side effect, this tutorial provides you with a (synthesizable) AXI4 Stream master which I have not seen provided by Xilinx. The closest IP provided by Xilinx, that I know of, is an AXI memory mapped to AXI stream block. Continue reading...

"Xilinx announced today that its Spartan-7 family of FPGAs is now available for order and shipping to standard lead times. As a key member of Xilinx's Cost-Optimized Portfolio, this device family is designed to meet the needs of cost-sensitive markets by delivering low cost and low power entry points that are I/O optimized for connectivity with industry leading performance-per-watt" For more information: Spartan-7 general availability announcement Spartan-7 device page

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Dual Tone Multi-Frequency (DTMF) is a method for encoding and decoding up to sixteen digits and special characters to be sent over a voice channel. DTMF was first developed by Bell Systems in United States, for use in push-button dialing telephones (in constrant to prior phones, which had a mechanic rotary dialing system). DTMF is standardized by ITU-T Recommendation Q.23 A DTMF keypad consists of a matrix of sixteen push buttons organized in four rows by four columns. Each button, when pressed, generates a pair of tones. The tones belong to two groups, a low frequency group (697 to 941 Hz) and a high frequency group (1209 to 1633 Hz). On the picture below you can see the buttons and associated frequencies: Pressing an '8' generates two tones, one low frequency tone of 852 Hz and one high frequency tone of 1336Hz. The frequencies were selected so no one would be an harmonic of another DTMF frequency. As it usually is for many digital transmission systems, the enc...

In the first part of this tutorial , we commented about the implementation of a single timer. The second part presented the implementation of a register based timers block, In this (third) part of the tutorial we will see a different way to implement the timers block. The timers block is a rather thirsty animal, let's see how many resources it needs for several configurations: Quantity of LUT Quantity of FF Single 32 bit timer 43 33 16 x 32 bit timers block 704 528 32 x 32 bit timers block 1,408 1,056 32 x 64 bit timers block 2,848 2,080 These numbers can be obtained by changing the DATA_W and TIMERS parameters on the VHDL package file and running synthesis for each configuration. After synthesis, in Vivado, we can get the number of used resources by taking a look at "Report utilization...

Block RAM memory - Source: Xilinx This post is now hosted here

Adam Taylor is the well known author of the MicroZed Chronicles blog on Xilinx website. His Chronicles have been running for several years, and Adam has already compiled entries from his blog in two books. The first book is offered for free on the FPGARelated website for registered users. This is a partial list of the book contents: Introduction to the Zynq Software environment and configuration The Boot loader XADC Multiplexed IO Timers, clocks and watchdogs Processing System and Programmable Logic DMA Adding an Operating System MultiProcessing etc. The book can be find here . Author Adam Taylor is a regular contributor on Xilinx Xcell Daily Blog  and he also has his own website .

Image source: Xilinx "Xilinx today announced that its high-performance Xilinx® Virtex® UltraScale+™ FPGAs are available in Amazon Elastic Compute Cloud (Amazon EC2) F1 instances. This instance provides programmable hardware acceleration with FPGAs and enables users to optimize their compute resources for the unique requirements of their workloads... ... F1 instances will be used to solve complex science, engineering, and business problems that require high bandwidth, enhanced networking, and very high compute capabilities. They are particularly beneficial for applications that are time sensitive such as clinical genomics, financial analytics, video processing, big data, security, and machine learning. " The Virtex Ultrascale+ family is based on the new  16 nm FinFET+  technology, and has the following features: Up to 8GB of HBM Gen2 integrated in-package  Up to 500Mb of on-chip memory integration  Integrated  100G Ethernet MAC  with RS-FEC ...

Wind turbines over the years - Infographic source: Dong Energy A/S

On the following three-part tutorial, a square waveform generator is presented. The requirements for the project are to generate a sequence of square waveforms with different frequencies. For each frequency a number of cycles is generated (different for each one). For each frequency, a distinct duty cycle is also defined. In this implementation the frequency is defined in Hz., and the active high time in ns. The VHDL code does not validate the parameters, i.e, if the active high time for any frequency is longer than its period, the output will be always '1' for that frequency. For each frequency, a number of cycles is defined. This project was born over a discussion in Xilinx forums . Once I did the project for a specific configuration I started thinking about a way to make a generic solution, and this tutorial tries to reflect the design process of this small project. The code is presented below. Three different frequencies FREQ1..3 are defined for this example, 242KHz...

Big Gross (himself an entrepreneur who has founded quite a few startups) analyzes the main reasons for success and failure of startups, and pinpoints a surprising main reason for that.

The comics strip says it all... ... or maybe not. There are so many missing: Ethernet, Fast Ethernet, Gigabit Ethernet The diverse Windows versions... and Unix, and Linux Serial Rapid IO, Infiniband PDAs, disc-man, MP3-player, tablets, digital cameras ADSL, optic fiber, and so many others... BTW, I first thought about this comics strip while reading about IoT. Will it be a success or will it be forgotten? I remember that in its time, ATM was also thought to be "the next thing, for sure". Well, it didn't happen... What would your list have?

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On the previous entry of this series we went through the VHDL source file and simulation of a Timer component. In this entry, we will instantiate several Timer components to create a timer bank (or block of timers). For this purpose we will instantiate the 'Timer' component presented on the first part of the tutorial several times. The instantiation is done inside a VHDL construct called a FOR GENERATE loop (see lines 50 - 61). The code is attached below: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; use work.top_pack.all ; entity top_timer_blk is port ( clk : in std_logic ; rst : in std_logic ; -- inputs data_in : in std_logic_vector (DATA_W - 1 downto 0 ); -- Data bus, connected to all timers load : ...