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Showing posts with the label news

Spartan 7 now available

"Xilinx announced today that its Spartan-7 family of FPGAs is now available for order and shipping to standard lead times. As a key member of Xilinx's Cost-Optimized Portfolio, this device family is designed to meet the needs of cost-sensitive markets by delivering low cost and low power entry points that are I/O optimized for connectivity with industry leading performance-per-watt" For more information: Spartan-7 general availability announcement Spartan-7 device page

Xilinx Announces General Availability of Virtex UltraScale+ FPGAs in Amazon EC2 F1 Instances

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Image source: Xilinx "Xilinx today announced that its high-performance Xilinx® Virtex® UltraScale+™ FPGAs are available in Amazon Elastic Compute Cloud (Amazon EC2) F1 instances. This instance provides programmable hardware acceleration with FPGAs and enables users to optimize their compute resources for the unique requirements of their workloads... ... F1 instances will be used to solve complex science, engineering, and business problems that require high bandwidth, enhanced networking, and very high compute capabilities. They are particularly beneficial for applications that are time sensitive such as clinical genomics, financial analytics, video processing, big data, security, and machine learning. " The Virtex Ultrascale+ family is based on the new  16 nm FinFET+  technology, and has the following features: Up to 8GB of HBM Gen2 integrated in-package  Up to 500Mb of on-chip memory integration  Integrated  100G Ethernet MAC  with RS-FEC ...

Size of wind turbines over the years

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Wind turbines over the years - Infographic source: Dong Energy A/S

Xilinx announces new RFSoC devices

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On February 21st Xilinx announced new devices aimed for the design of solutions for 5G wireless systems. The announced RFSoC devices will combine existing MPSoC capabilities with integrated ADCs and DACs. The integrated 16nm-based RF data conversion technology includes: Direct RF sampling 12-bit ADCs at up to 4GSPS, with digital down-conversion 14-bit DACs at up to 6.4GSPS, with digital up-conversion Current solutions for SDR are typically based on superhet transceivers. The superhet architecture needs: IF stage including a Local Oscillator for mixing High speed converters, typically needing fast SerDes (JESD204) to interconnect the processing FPGA to the ADC and DAC Direct RF Sampling Receiver - Source: Xilinx Xilinx proposed architecture with integrated DAC and ADC as well as direct RF sampling simplifies and enhances the SDR solution implementation: Reduced noise Reduced power consumption Reduced PCB size and routing complexity As of the date ...