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Square waveform generator

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On the following three-part tutorial, a square waveform generator is presented. The requirements for the project are to generate a sequence of square waveforms with different frequencies. For each frequency a number of cycles is generated (different for each one). For each frequency, a distinct duty cycle is also defined. In this implementation the frequency is defined in Hz., and the active high time in ns. The VHDL code does not validate the parameters, i.e, if the active high time for any frequency is longer than its period, the output will be always '1' for that frequency. For each frequency, a number of cycles is defined. This project was born over a discussion in Xilinx forums . Once I did the project for a specific configuration I started thinking about a way to make a generic solution, and this tutorial tries to reflect the design process of this small project. The code is presented below. Three different frequencies FREQ1..3 are defined for this example, 242KHz...

Signed, unsigned and std_logic_vector

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