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On the previous entry of this series we went through the VHDL source file and simulation of a Timer component. In this entry, we will instantiate several Timer components to create a timer bank (or block of timers). For this purpose we will instantiate the 'Timer' component presented on the first part of the tutorial several times. The instantiation is done inside a VHDL construct called a FOR GENERATE loop (see lines 50 - 61). The code is attached below: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; use work.top_pack.all ; entity top_timer_blk is port ( clk : in std_logic ; rst : in std_logic ; -- inputs data_in : in std_logic_vector (DATA_W - 1 downto 0 ); -- Data bus, connected to all timers load : ...

Hi. In this series of articles, we will experiment with the definition, implementation, simulation and synthesis of a block of timers in VHDL. Along the way, we will: Test the VHDL code blocks using Vivado simulator. Synthesize and implement the VHDL code on Xilinx's Zynq FPGA. Originally this project was used on a relatively small FPGA. The logic for the timers didn't fit so I used the internal memory to implement the solution. In many of my designs I have seen that it is the LUTs (and not the FFs or the internal RAM) what tends to be under heavy utilization. So using the block RAM to implement register (or timers) banks can be a way to fit a design into a device. So first, let's start with the code for a single timer component: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; entity...

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