tag:blogger.com,1999:blog-63683395557437114212024-03-05T21:43:16.920+02:00FPGA SiteFPGA projects in VHDL. VHDL tutorials. VHDL code snippets. VHDL free bookschclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.comBlogger44125tag:blogger.com,1999:blog-6368339555743711421.post-59858246090964668242022-10-11T22:53:00.000+03:002022-10-11T22:53:04.550+03:00VHDL arbiters - part III <p style="box-sizing: inherit; font-family: "Exo 2", sans-serif; font-size: 16px; margin: 0px 0px 24px;"><span style="background-color: white;">This is the third part of a series of articles on VHDL arbiters.</span></p><p style="box-sizing: inherit; font-family: "Exo 2", sans-serif; font-size: 16px; margin: 0px 0px 24px;"><span style="background-color: white;">In the <a href="https://fpgaer.tech/?p=533" style="box-sizing: inherit; color: #1985a1; font-weight: 700; text-decoration-line: none;">first part</a>, we commented on what a VHDL arbiter is.</span></p><p style="box-sizing: inherit; font-family: "Exo 2", sans-serif; font-size: 16px; margin: 0px 0px 24px;"><span style="background-color: white;">In the <a href="https://fpgaer.tech/?p=542" style="box-sizing: inherit; color: #1985a1; font-weight: 700; text-decoration-line: none;">second part</a>, we saw the VHDL code for a fixed-priority VHDL arbiter.</span></p><p style="box-sizing: inherit; font-family: "Exo 2", sans-serif; font-size: 16px; margin: 0px 0px 24px;"><span style="background-color: white;">When I talked about what a VHDL arbiter is, I gave the example of the single car we have at home, and how I have to decide who gets to use the car next Friday evening. In a typical situation, if both children ask for the car, the first thing they will account for is, who got the car the last time.</span></p><p style="box-sizing: inherit; font-family: "Exo 2", sans-serif; font-size: 16px; margin: 0px 0px 24px;"><a href="https://fpgaer.tech/?p=622" style="background-color: white; box-sizing: inherit; color: #1985a1; font-weight: 700; text-decoration-line: none;">Continue reading…</a></p><div><br /></div><div id="atatags-370373-6345c984afcb1" style="background-color: #dcdcdd; box-sizing: inherit; font-family: "Exo 2", sans-serif; font-size: 16px;"></div><div class="wpcnt" id="wordads-preview-parent" style="background-color: #dcdcdd; box-sizing: inherit; font-family: "Exo 2", sans-serif; font-size: 16px; line-height: 0; text-align: center;"><div class="wpa" style="box-sizing: inherit; display: inline-block !important; max-width: 100%; position: relative; text-align: left; transform: translate3d(0px, 0px, 0px);"></div></div>chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-43385894202609744072018-05-05T09:39:00.006+03:002022-10-01T19:34:30.642+03:00Newer updates<h2 style="clear: both; text-align: center;">FPGASite is alive and kicking!</h2><div><br /></div>(We just changed our website address).<br /><br />The new blog has several new articles and features, in addition to actualizations of articles that were hosted in the past on this website.<br /><br />Examples:<br /><br />A series of <a href="https://fpgaer.tech/?cat=53">articles and projects</a> for Digilent’s Basys 3 board (using an Artix-7 FPGA from Xilinx)<br /><br />New <a href="https://fpgaer.tech/?cat=15">technical articles</a> and <a href="https://fpgaer.tech/?page_id=129">code snippets</a>, among them:<div><ul style="text-align: left;"><li><a href="https://fpgaer.tech/?p=447">AXI-Lite registers bank</a></li><li><a href="https://fpgaer.tech/?p=289">Xilinx AXI Chip2Chip for multi-FPGA designs</a></li></ul>… and many more!<br /><br />And a selection of legally <a href="https://fpgaer.tech/?page_id=454">free books</a> on FPGAs, VHDL, Machine Learning, Verification, etc.</div><div><br /><div style="text-align: center;">See you there, at the new <a href="http://fpgaer.tech">FPGA'er website</a>:</div>
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<br />chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-18955273491314242352017-09-20T09:56:00.004+03:002022-09-02T21:44:57.073+03:00Understanding Machine Learning - free book<div class="separator" style="clear: both; text-align: center;">
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chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-13643220028479504152017-09-16T09:39:00.001+03:002017-09-17T06:54:19.125+03:00Organizing your tasks, and design files<div style="text-align: right;">
<em>Men marry women wishing they will never change, but they do.</em><br />
<em>Women marry men wishing they will be able to change them, but they don't.</em></div>
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When I was young, even during my University studies, I was a real disaster in anything related to order and tidiness. My room was always a mess. Whenever my mother or any other would try to change my ways (even a little bit), I would say what many like me love to say: - "In the disorder, I know where everything is. When my mother makes some order, I can't find anything".<br />
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And to demonstrate that the half-joke at the beginning of this article is not true, I must say that I changed a lot since I married. My home won't appear in a decoration magazine, but it is not close at all to my young-days' complete-mess room.<br />
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The other reason I have to train me all the time to be a more tidy person is that I work in FPGA design. So if you are rolling your eyes thinking that order has nothing to do with design, and I'd better publish some interesting VHDL tips instead of all this "be tidy" nonsense... hang with me a bit more, and I hope I can convince you.<br />
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If, on the other hand, you are rolling your eyes because for you it is OBVIOUS that order and method are needed... keep reading, maybe you can learn a pair of tips to improve your order.<br />
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<h2>
<strong>Keeping your files organized</strong></h2>
To keep your files organized, the method is really very simple. You make a directory tree with categories for each one of the files types needed for your design.<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgE_lWe-Vzg2ma4fciGt0CRPFG8Fgp5k1LX7UWgD3IedZ47D0cKEzH64rWAT35gpoPT3J6rjIVPVagY2Z-wQtIuEx2D_-ZCYxh5Kxixqj4-D79VKZnaInth_4sJJn0XgON_appN1-PxjA/s1600/directory_tree+%25281%2529.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="216" data-original-width="578" height="148" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgE_lWe-Vzg2ma4fciGt0CRPFG8Fgp5k1LX7UWgD3IedZ47D0cKEzH64rWAT35gpoPT3J6rjIVPVagY2Z-wQtIuEx2D_-ZCYxh5Kxixqj4-D79VKZnaInth_4sJJn0XgON_appN1-PxjA/s400/directory_tree+%25281%2529.png" width="400" /></a></div>
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The above screenshot is an example of how I organize projects in my hard disk. The categories are not mandatory, you may want more or less.<br />
<b>docs </b>- documents, pictures, specs, datasheets<br />
<b>hdl </b>- all synthesizable HDL source files (VHDL and/or Verilog). Of course, as the design grows, this will be divided in sub-directories, one for each module. And some other, one for common files and packages for all modules, one for Altera IP's, etc.<br />
<b>matlab </b>- for formal verification of the design<br />
<b>quartus </b>- here I synthesize the design using Altera tools (adapt to your preferred manufacturer)<br />
<b>sim </b>- Simulations. Here I configure Modelsim to drop all its files<br />
<b>tb </b>- Testbench files used together with Modelsim<br />
<h3>
<strong>The most important target to achieve is to update your files in a single place. </strong></h3>
I don't change any source that is part of the design in no place other than the 'hdl' directory. When I setup the simulation, I instruct Modelsim to take its source files from hdl. Quartus is also instructed to take the files from there. And I have a single point of update. If you don't do something like this, try it. It will save you a lot of headaches.<br />
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<strong>The second target to achieve is to keep key directories clean.</strong></h3>
Quartus, Modelsim and other design tools tend to produce lots of bulky files. If you let those tools drop their files together with your source files, soon maintaining your design will become a nightmare.<br />
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<strong>The third target to achieve is ease of backup.</strong></h3>
If you separate your folders, when you make backups (and you should, frequently) it is easy to separate the relatively small source files from the bulky reports from Synthesis or waveforms from simulation. These days there is no excuse at all not to make many backups, as many as you can, using disk-on-key, the cloud and version management tools like Clear Case, SVN or GIT.<br />
Each time you make a new backup, give it a new number and keep a read.me file at the root of the backup folder stating the date of the backup and major features of this version/bugs solved/bugs pending and any other useful information.<br />
Version management tools usually provide logs/text for version tracking. Personally I find easier to track my major version features and to-dos on the read.me file, but you may find easier to use the features of your version management tool.<br />
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<h2>
<strong>Keeping track of your tasks</strong></h2>
Call me old. I still have and use design notebooks. Each time I go to a meeting I write down everything I can. I tend to forget a lot of things unless I write them down. I also write date, project, and main points and decisions of the meeting. I know, the organizer should send a meeting summary. So he/she should. In my country, many times that simply doesn't happen or if it happens, it has a lot of information holes on it.<br />
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When my boss or my client asks for something, I add it to a note or to my notebook. When I am back at my computer, I update my TO DO list. I have one list for each projects, with three or four columns.<br />
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<li style="text-align: left;"><strong>Title</strong>,</li>
<li style="text-align: left;"><strong>Description</strong>,</li>
<li style="text-align: left;"><strong>Done</strong>, and</li>
<li style="text-align: left;"><strong>Remarks</strong></li>
</ul>
When I complete a task I mark the third column, which in itself is a nice thing to do. Nothing like dropping some weight from your shoulders. And your boss/client will love not having to ask you for a specific task to complete, again and again.<br />
Now is your turn. I would love to hear your tips to keep the job done, your files organized, and your day productive.<br />
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<br />chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-65073072943981509182017-09-13T06:31:00.001+03:002017-09-16T12:34:30.834+03:00Giant Hovercrafts - past and future<iframe allowfullscreen="" frameborder="0" height="354" src="https://www.youtube.com/embed/Inog40YZcYs" width="600"></iframe>
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<br />chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-15582898579622280552017-09-12T06:21:00.002+03:002022-10-11T22:48:13.244+03:00VHDL arbiters - part II<div style="text-align: center;"><div class="entry-content" style="box-sizing: inherit; font-family: "Exo 2", sans-serif; font-size: 16px; margin: 24px 0px 0px; text-align: start;"><p style="box-sizing: inherit; margin: 0px 0px 24px;"><span style="background-color: white;">In the <a href="https://fpgaer.tech/?p=533" style="box-sizing: inherit; color: #1985a1; font-weight: 700; text-decoration-line: none;">first article of this series</a>, we defined what an HW arbiter is.<br style="box-sizing: inherit;" />In this entry of the tutorial, we will see a simple implementation of a VHDL arbiter.</span></p><p style="box-sizing: inherit; margin: 0px 0px 24px;"><span style="background-color: white;">The arbiter of this example has three request inputs and three grant outputs. It has a fixed priority for the masters. The lower the master number, the higher its priority.<br style="box-sizing: inherit;" />The block also has a <span style="box-sizing: inherit; font-weight: 700;"><em style="box-sizing: inherit;">busy</em></span> signal. Arbitration of the bus is done only while it is inactive. If the bus has already been granted to an agent, even if a bigger priority master requests the bus, the current transaction must complete before the arbiter grants the bus to another master.</span></p></div><p style="box-sizing: inherit; font-family: "Exo 2", sans-serif; font-size: 16px; margin: 0px 0px 24px; text-align: left;"><a href="https://fpgaer.tech/?p=542" style="background-color: white; box-sizing: inherit; color: #1985a1; font-weight: 700; text-decoration-line: none;">Continue reading…</a></p></div>
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<div style="text-align: right;"><br /></div>chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-30746475245066239362017-09-11T20:49:00.002+03:002022-09-02T21:47:39.024+03:00FPGA for dummies - free book<div class="separator" style="clear: both; text-align: center;">
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<br />This post is now hosted <a href="https://fpgaer.tech/?p=191">here</a>chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-47792974161293220972017-09-09T22:24:00.000+03:002017-09-10T19:58:47.533+03:00MIF_Gen - A Matlab Utility<div class="separator" style="clear: both; text-align: center;">
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Many times I find myself in the need of generating data for testing. We need data for verification, either done on simulation or on the real target.<br />
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One easy way to test our system is to generate data vectors on RAM. Altera RAM IP includes the ability to initialize RAM contents during power-up by means of a .hex file.<br />
One problem of the .hex file format is that it is quite unreadable for humans. Altera came to our rescue with the .mif format, which is text based and very easy to understand.<br />
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The application I present below initializes a memory (generating an .hex file). The size and width of the memory are parameters. The Matlab application generates both a init_mem.mif and a init_mem.hex file.<br />
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52</pre>
</td><td><pre style="line-height: 125%; margin: 0;"> <span style="color: #888888;">%-------------------------------------------</span>
<span style="color: #888888;">% Generate Parameters</span>
ram_size = <span style="color: #0000dd; font-weight: bold;">256</span>; <span style="color: #888888;">% In words</span>
word_size = <span style="color: #0000dd; font-weight: bold;">16</span>; <span style="color: #888888;">% Can be 8, 16, 32, etc. </span>
<span style="color: #888888;">%-------------------------------------------</span>
<span style="color: #888888;">% generate vector with random values within </span>
<span style="color: #888888;">% a defined range</span>
min_v = <span style="color: #0000dd; font-weight: bold;">100</span>;
max_v = <span style="color: #0000dd; font-weight: bold;">20000</span>;
<span style="color: #888888;">% Check values and calculate range</span>
<span style="color: #008800; font-weight: bold;">if</span> (min_v <span style="color: #333333;"><</span> <span style="color: #0000dd; font-weight: bold;">0</span>)
min_v = <span style="color: #0000dd; font-weight: bold;">0</span>;
<span style="color: #008800; font-weight: bold;">end</span>
max_val = <span style="color: #0000dd; font-weight: bold;">2</span>^word_size<span style="color: #333333;">-</span><span style="color: #0000dd; font-weight: bold;">1</span>;
<span style="color: #008800; font-weight: bold;">if</span> (max_v <span style="color: #333333;">></span> max_val)
max_v = max_val;
<span style="color: #008800; font-weight: bold;">end</span>
range_v = max_v <span style="color: #333333;">-</span> min_v;
values = (randi(range_v <span style="color: #333333;">-</span> <span style="color: #0000dd; font-weight: bold;">1</span>, ram_size, <span style="color: #0000dd; font-weight: bold;">1</span>)) <span style="color: #333333;">+</span> min_v;
<span style="color: #888888;">%-------------------------------------------</span>
<span style="color: #888888;">% Open mif file for write</span>
fileID = fopen(<span style="background-color: #fff0f0;">'init_mem.mif'</span>, <span style="background-color: #fff0f0;">'w'</span>);
fprintf( fileID, <span style="background-color: #fff0f0;">'%s\n'</span>, <span style="background-color: #fff0f0;">'-- Generated by mif_gen Matlab script'</span>);
fprintf( fileID, <span style="background-color: #fff0f0;">'%s\n\n'</span>, <span style="background-color: #fff0f0;">'-- FPGA SITE - https://fpgasite.blogspot.com'</span>);
fprintf( fileID, <span style="background-color: #fff0f0;">'%s%d%s\n'</span>, <span style="background-color: #fff0f0;">'WIDTH='</span>, word_size, <span style="background-color: #fff0f0;">';'</span>);
fprintf( fileID, <span style="background-color: #fff0f0;">'%s%d%s\n\n'</span>, <span style="background-color: #fff0f0;">'DEPTH='</span>, ram_size, <span style="background-color: #fff0f0;">';'</span>);
fprintf( fileID, <span style="background-color: #fff0f0;">'%s\n'</span>, <span style="background-color: #fff0f0;">'ADDRESS_RADIX=HEX;'</span>);
fprintf( fileID, <span style="background-color: #fff0f0;">'%s\n\n'</span>, <span style="background-color: #fff0f0;">'DATA_RADIX=HEX;'</span>);
fprintf( fileID, <span style="background-color: #fff0f0;">'%s\n'</span>, <span style="background-color: #fff0f0;">'CONTENT BEGIN'</span>);
<span style="color: #888888;">% data format</span>
fdata = int2str(word_size<span style="color: #333333;">/</span><span style="color: #0000dd; font-weight: bold;">4</span>);
faddr = int2str(<span style="color: #007020;">log2</span>(ram_size)<span style="color: #333333;">/</span><span style="color: #0000dd; font-weight: bold;">4</span>);
format_str = strcat(<span style="background-color: #fff0f0;">' %0'</span>, faddr, <span style="background-color: #fff0f0;">'X : %0'</span>, fdata, <span style="background-color: #fff0f0;">'X;\n'</span>);
<span style="color: #888888;">% write values to file</span>
idx = <span style="color: #0000dd; font-weight: bold;">0</span>;
<span style="color: #008800; font-weight: bold;">for</span> ii=<span style="color: #0000dd; font-weight: bold;">1</span>:ram_size
fprintf( fileID, format_str, idx, values(idx<span style="color: #333333;">+</span><span style="color: #0000dd; font-weight: bold;">1</span>));
idx = idx<span style="color: #333333;">+</span><span style="color: #0000dd; font-weight: bold;">1</span>;
<span style="color: #008800; font-weight: bold;">end</span>
fprintf( fileID, <span style="background-color: #fff0f0;">'%s\n'</span>, <span style="background-color: #fff0f0;">'END;'</span>);
fclose( fileID);
<span style="color: #888888;">%-------------------------------------------</span>
<span style="color: #888888;">% Convert to HEX</span>
cmd = <span style="background-color: #fff0f0;">'D:\altera_lite\15.1\quartus\bin64\mif2hex keys.mif init_mem.hex'</span>;
system(cmd);
</pre>
</td></tr>
</tbody></table>
</div>
<br />
Lines 26 to 33 generate Altera .mif header. Lines 36 to 38 define the format for writing the data rows with the fprintf command, based on the memory size and width.<br />
<br />
Lines 41 to 47 actually put the values on each line of the file.<br />
<br />
Lines 51 and 52 generate the .hex file via a system call using Altera's mif2hex utility. You will need to change the path on line 72 to the actual location of your Quartus installation.<br />
<br />
<div style="text-align: justify;">
<div style="text-align: right;">
<i><b>This utility is available at <a href="https://github.com/chclau/MIF_Gen/releases/tag/v1.0">Github</a></b></i></div>
</div>
chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-5882470093989252412017-09-09T16:01:00.004+03:002022-10-07T18:11:40.286+03:00VHDL arbiters<h2>
What is an arbiter?</h2><div><h2 style="background-color: white; box-sizing: inherit; clear: both; color: #222222; font-family: "Open Sans", serif; font-size: 32px; line-height: 1.125; margin-bottom: 24px; margin-top: 0px;">What is an arbiter?</h2><p style="background-color: white; box-sizing: inherit; color: #222222; font-family: Lora, serif; font-size: 16px; margin: 0px 0px 24px;">An arbiter is a very common block used on HW designs.</p><p style="background-color: white; box-sizing: inherit; color: #222222; font-family: Lora, serif; font-size: 16px; margin: 0px 0px 24px;">I think I can find the best example of an arbiter at home. When my two kids were teenagers, I had only one car. On Friday and Saturday evenings, there was usually a conflict over who got to use the car. Usually, it was on me to decide (arbiter) who got the car. Not an easy task. (I still have only one car. It just happens that my kids are not teenagers anymore, and praise the Lord, they have their own cars).</p></div><h2><p style="text-align: left;"><span style="font-weight: normal;"><a href="https://fpgaer.tech/?p=533">Continue reading...</a> </span></p><div class="separator" style="clear: both; text-align: center;"><br /></div>
</h2><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhhdg8HlOWSj-_x9VgU7w8JvKjykCSf4wbVY9-vpcN4uac6iQ9brdFHUnRyAH0HvnionXPwBnT_iXKF6RHsexK8NM7PntkqfTJFH9R2MLtAElzcUMFSph7YhbALajY15DmPWGtZ5nstwA/s1600/fpgaer8_1.png" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="506" data-original-width="419" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhhdg8HlOWSj-_x9VgU7w8JvKjykCSf4wbVY9-vpcN4uac6iQ9brdFHUnRyAH0HvnionXPwBnT_iXKF6RHsexK8NM7PntkqfTJFH9R2MLtAElzcUMFSph7YhbALajY15DmPWGtZ5nstwA/s1600/fpgaer8_1.png" /></a></div>
chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-982577226129402232017-09-08T16:03:00.004+03:002017-09-08T16:03:53.303+03:00FPGAs and Deep Machine Learning<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiPeiw2yBt9edVazsgz28M_dQRUKPTpnaRHlKBgqWDcuST7Au5t97M5hkeXXpUVJzbso0pBSzz4b9yhRcLSIMWxkbQ_L_BxrVWFRs1zbV9syWCMxx42S08DlH2hg6WgqYpY5TOLzOfaTA/s1600/machine-learning.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="510" data-original-width="680" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiPeiw2yBt9edVazsgz28M_dQRUKPTpnaRHlKBgqWDcuST7Au5t97M5hkeXXpUVJzbso0pBSzz4b9yhRcLSIMWxkbQ_L_BxrVWFRs1zbV9syWCMxx42S08DlH2hg6WgqYpY5TOLzOfaTA/s1600/machine-learning.jpg" /></a></div>
<br />
The concept of machine learning is not new. Attempts at systems emulating intelligent behavior, like expert systems, go as far back as the early 1980's. And the very notion of modern Artificial Intelligence has a long history. The name itself was coined at a Dartmouth College conference (1956), but the idea of an "electronic brain" was born together with the development of modern computers. AI as an idea accompanies us from the dawn of human history.<br />
Three latest development are pushing forward "Machine Learning":<br />
<ul>
<li>Powerful distributed processors</li>
<li>Cheap and high volume storage</li>
<li>High bandwidth interconnection to bring the data to the processors</li>
</ul>
<div>
As in many other fields, development of Machine Learning is also seeing development on algorithms that take advantage of the new hardware capabilities.<br />
There are four types of algorithms used in machine learning:<br />
<ul>
<li>Supervised - The vast majority of systems today. These systems are 'trained' based on past data on an attempt to predict future outcomes.</li>
<li>Unsupervised - These systems try to build models, by themselves, of the process analyzed.</li>
<li>Semi supervised - is a combination of the first two, where a small amount of data is 'labeled' (i.e. related to known training rules) and the machine uses this as a seed to label the rest of the data</li>
<li>Reinforcement - The algorithm creates its rules through trial and error.</li>
</ul>
<br />
According Wikipedia, Deep Learning is "a part of a broader family of <a href="https://en.wikipedia.org/wiki/Machine_learning" title="Machine learning">machine learning</a> methods based on <a class="mw-redirect" href="https://en.wikipedia.org/wiki/Learning_representation" title="Learning representation">learning representations</a> of data. An observation (e.g., an image) can be represented in many ways such as a <a href="https://en.wikipedia.org/wiki/Vector_space" title="Vector space">vector</a> of intensity values per pixel, or in a more abstract way as a set of edges, regions of particular shape, etc. Some representations are better than others at simplifying the learning task".<br />
For Neural Network based implementations, Deep Machine Learning solutions have many hidden neural layers.<br />
<br />
Until recently, most Deep Learning solutions were based on the use of GPUs. However, FPGAs are being seen as a valid alternative for GPU based Deep Learning solutions.<br />
The main reason for that is the lower cost and lower power consumption of FPGAs compared to GPUs in Deep Learning applications.</div>
<br />
<hr />
<table style="width: 100%;">
<tbody>
<tr>
<td><a href="https://www.facebook.com/groups/576882062479011/" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;" target="_blank"><img border="0" data-original-height="234" data-original-width="350" height="213" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiqPvKLV3-rcYz_B-wVAWan5A25JxKR1hWwuHBYH6bSLykuZkDvXNkpfJUUdLi9rfYNqtzla7Lnz43tAIDhG9LediFUVvo3eI1cKNaQUYhvaZHoEbmfg9HTfMS-KlNyfubO4ycLBGzj7g/s320/fb_disc_grp.jpg" width="320" /></a>
</td>
<td><a href="https://www.linkedin.com/groups/7064275" target="_blank"><img border="0" data-original-height="222" data-original-width="220" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEic0J26GEat_wa4Udi9j7E3b1zSUCCVcrNMXjlDXaWdeGD4VHl9WEIDNmM2497ZLhSUYbuvhJCjV5a16-SBNeXxIgE2Jwo_kbjIwE6MtzR3hJH_KXN7AzGveoqI4cFbWBBUWwLGJmu4TQ/s1600/grp_linkedin.jpg" /></a></td>
</tr>
</tbody></table>
<hr />
<a href="https://www.microsoft.com/en-us/research/machine-learning-gets-big-boost-from-ultra-efficient-convolutional-neural-network-accelerator/">Microsoft</a> adopted Intel-Altera Arria 10 devices for their Convolutional Neural Network (CNNs), estimating that the usage of FPGAs would increase their system throughput roughly at 70% with the same power consumption.<br />
<br />
A recent article on Next Platform comments on how <a href="http://www.nextplatform.com/2016/08/23/fpga-based-deep-learning-accelerators-take-asics/">Baidu</a> has also adopted FPGAs for deep learning solutions.<br />
<br />
<a href="http://www.teradeep.com/">Teradeep</a> is another company (startup) developing CNNs, and one among the first of those adopting FPGAs as an alternative to GPUs. In May this year Xilinx announced it invested in Teradeep and continue working closely together to optimize its technology.<br />
<br />
For some time Intel-Altera has been pushing <a href="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/solution-sheets/efficient_neural_networks.pdf">OpenCL </a>for the implementation of Neural Networks. New devices from Altera and Xilinx are specifically oriented for distributed processing applications, efficient integration of FPGAs with high end processors and/or high bandwidth throughput (on-dice DDR devices with high throughput links to the FPGA logic core).chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com1tag:blogger.com,1999:blog-6368339555743711421.post-68961517324753498062017-09-08T12:49:00.001+03:002017-09-08T12:49:45.373+03:00Guinness - GUI based Neural Network Synthesizer<div style="text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg_dURqUK_KKyrEUk1JWR-qzzWftdnjyngoDwWNWbSD3KbzltpnwPqPPCvGjAFbUyCYES7uEiv8OYkQ2Zk7dZnIjZoV3YvcuO81qhw5HMUFt_HG4KG5O-FpYhFV62uN3AMU1gjOEzwaPQ/s1600/mach_learn.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="724" data-original-width="1024" height="282" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg_dURqUK_KKyrEUk1JWR-qzzWftdnjyngoDwWNWbSD3KbzltpnwPqPPCvGjAFbUyCYES7uEiv8OYkQ2Zk7dZnIjZoV3YvcuO81qhw5HMUFt_HG4KG5O-FpYhFV62uN3AMU1gjOEzwaPQ/s400/mach_learn.jpg" width="400" /></a>
<br />
<br />
<div style="text-align: justify;">
<span style="background-color: white; color: #24292e; font-size: 16px;"><span style="font-family: inherit;">Guinness is a GUI based framework that includes both a training on a GPU, and a bitstream generation for an FPGA using the Xilinx SDSoC. This tool uses the Chainer deep learning framework to train a binarized CNN. Also, it uses optimization techniques for an FPGA implementation.</span></span></div>
</div>
<div style="text-align: center;">
<div style="text-align: justify;">
<span style="font-family: inherit;"><br /></span></div>
<div style="text-align: justify;">
<span style="background-color: white; color: #333333; font-size: 15px;"><span style="font-family: inherit;">Compared with the conventional FPGA realizations, although the classification accuracy is 6.5% decayed, the performance is 2.45 times faster, the power efficiency is slightly better, and the area efficiency is 2.68 times better. Compared with the ARM Cortex-A57, it is 136.8 times faster, it dissipates 3.1 times much power, and its performance per power efficiency is 44.7 times better. Also, compared with the Maxwell embedded GPU, it is 4.9 times faster, it dissipates 1.3 times much power, and its performance per power efficiency is 3.8 times better. </span></span></div>
<div style="text-align: justify;">
<span style="font-family: inherit;"><br /></span></div>
<div style="text-align: justify;">
<span style="background-color: white; color: #24292e; font-size: 16px;"><span style="font-family: inherit;">Details are shown in following papers:</span></span></div>
<div style="text-align: justify;">
<span style="background-color: white; color: #24292e; font-size: 16px;"><span style="font-family: inherit;"><br /></span></span></div>
<div style="text-align: justify;">
<span style="font-family: inherit;"><span style="background-color: white; color: #24292e; font-size: 16px;">[Nakahara IPDPSW2017] H. Yonekawa and H. Nakahara, "On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA," IPDPS Workshops, 2017, pp. 98-105.</span><br style="background-color: white; box-sizing: border-box; color: #24292e; font-size: 16px; text-align: start;" /><span style="background-color: white; color: #24292e; font-size: 16px;">[Nakahara FPL2017] H. Nakahara et al., "A Fully Connected Layer Elimination for a Binarized Convolutional Neural Network on an FPGA", FPL, 2017, (to appear).</span></span></div>
<div style="text-align: justify;">
<span style="background-color: white; color: #24292e; font-size: 16px;"><span style="font-family: inherit;"><br /></span></span></div>
<div style="text-align: right;">
<a href="https://github.com/HirokiNakahara/GUINNESS" rel="nofollow noopener noreferrer" style="background-color: white; box-sizing: border-box; color: grey; font-size: 14px; outline: none !important; text-align: left;" target="_blank"><span style="font-family: inherit;"><i>Guinness is available on GitHub.</i></span></a></div>
<div style="text-align: right;">
<br /></div>
</div>
<div style="text-align: center;">
<div style="background-color: #e6fadc; background-image: none; box-sizing: border-box; color: #3d3d3d; font-size: 14px; outline: none; padding: 0px;">
</div>
</div>
chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-6985506400078458532017-08-06T03:59:00.001+03:002017-08-07T08:47:07.540+03:00SETI's FPGAs<div class="clearfix" id="watch7-headline" style="background-attachment: initial; background-clip: initial; background-image: initial; background-origin: initial; background-position: initial; background-repeat: initial; background-size: initial; border: 0px; font-family: "YouTube Noto", Roboto, arial, sans-serif; font-size: 13px; margin: 0px; padding: 0px;">
<div id="watch-headline-title" style="background-attachment: initial; background-clip: initial; background-image: initial; background-origin: initial; background-position: initial; background-repeat: initial; background-size: initial; border: 0px; margin: 0px; padding: 0px;">
<h1 class="watch-title-container" style="-ms-word-wrap: break-word; border-image: none; border: 0px currentColor; font-size: 20px; font-weight: normal; line-height: normal; margin: 0px; padding: 0px; width: 618px;">
<span class="watch-title" dir="ltr" id="eow-title" style="background-attachment: initial; background-clip: initial; background-image: initial; background-origin: initial; background-position: initial; background-repeat: initial; background-size: initial; border: 0px; margin: 0px; padding: 0px;" title="FPGAs and GPUs: a Tour of our Computer Hardware">FPGAs and GPUs: a Tour of SETI's Computer Hardware</span></h1>
<div>
<span class="watch-title" dir="ltr" style="background-attachment: initial; background-clip: initial; background-image: initial; background-origin: initial; background-position: initial; background-repeat: initial; background-size: initial; border: 0px; margin: 0px; padding: 0px;" title="FPGAs and GPUs: a Tour of our Computer Hardware"><br /></span></div>
<div class="separator" style="clear: both; text-align: center;">
<iframe allowfullscreen="" class="YOUTUBE-iframe-video" data-thumbnail-src="https://i.ytimg.com/vi/IOJ6-_gIyP0/0.jpg" frameborder="0" height="266" src="https://www.youtube.com/embed/IOJ6-_gIyP0?feature=player_embedded" width="320"></iframe></div>
<br />
<br />
David MacMahon is a research astronomer with Berkeley SETI Research Center. Dave works on several projects at BSRC, including Breakthrough Listen, designing many of the computer systems we use to process data collected from our telescopes. If you've ever been curious what hardware is required to search for ET, check out this tour of Berkeley SETI behind the scenes.<br />
<br /></div>
</div>
<br />
<hr />
<div class="separator" style="clear: both; text-align: center;">
<br /></div>
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg_HnQaZoddYAY0o4_V0S9zw0ChPsgXp5sAJtUoKIjaUMEsANDgSvpnvQdpyMF8WY0l-JK-8DNtCna5UORy-d6H4xnop8Elpd2pMeCb2MXMwIenv_DYTXsDAWSLFKaf-67H92NYX2-qyw/s1600/fpgaer5.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" data-original-height="522" data-original-width="468" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg_HnQaZoddYAY0o4_V0S9zw0ChPsgXp5sAJtUoKIjaUMEsANDgSvpnvQdpyMF8WY0l-JK-8DNtCna5UORy-d6H4xnop8Elpd2pMeCb2MXMwIenv_DYTXsDAWSLFKaf-67H92NYX2-qyw/s1600/fpgaer5.png" /></a></div>
chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-26006685088923623232017-08-06T02:12:00.000+03:002017-08-06T02:12:03.239+03:00Slight Street Sign Modifications Can Completely Fool Machine Learning Algorithms<table cellpadding="0" cellspacing="0" class="tr-caption-container" style="float: left; margin-right: 1em; text-align: left;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgEf36E1c_r1FF0PP1Cipmul-J-jDXE-Cjq6MoCaoqOWUsueqnqJaaBvWGuVcRlNqlAD3cE6OWl1TNs0nm6tu-Zvv6Nb55jjPC9CUVT7k2jmMnAVUWvW2bpdQWZfyIIghp6I0uF5DmmVA/s1600/mach_learn.jpg" imageanchor="1" style="clear: left; margin-bottom: 1em; margin-left: auto; margin-right: auto;"><img border="0" data-original-height="724" data-original-width="1024" height="226" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgEf36E1c_r1FF0PP1Cipmul-J-jDXE-Cjq6MoCaoqOWUsueqnqJaaBvWGuVcRlNqlAD3cE6OWl1TNs0nm6tu-Zvv6Nb55jjPC9CUVT7k2jmMnAVUWvW2bpdQWZfyIIghp6I0uF5DmmVA/s320/mach_learn.jpg" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Image Source: Linked In</td></tr>
</tbody></table>
Machine Learning is a hot I+D topic.<br />
<br />
One of the strategies used in Machine Learning is to learn by means of neural networks. You can get a free introduction to neural networks <a href="http://neuralnetworksanddeeplearning.com/" target="_blank">here</a>.<br />
I also warmly recommend Andrew Ng's introductory course to Machine Learning on <a href="https://www.coursera.org/learn/machine-learning" target="_blank">Coursera</a>.<br />
<br />
Machine Learning neural networks were inspired by biological neural networks, and are easily applied but highly effective in image processing algorithms, like handwritten text recognition.<br />
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More complex neural networks algorithms are being implemented on what is called Deep Machine Learning, using neural networks with many layers of complexity.<br />
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Typically a neural network is trained, or it learns, from its exposure to thousands of 'good' and 'bad' examples of the image to be recognized or classfied. For example, a neural network that has to recognize handwritten numbers, will be exposed to thousands of examples of numbers written by different people, and even with changes in the orientation of the texts.<br />
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In the past, <a href="https://arxiv.org/abs/1602.02697" target="_blank">some papers</a> have shown that neural networks can be easily attacked, or confused, by adding special filters to images. While those attacks cannot confuse humans at all, they easily defeat even deep learning neural networks.<br />
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In <a href="http://spectrum.ieee.org/cars-that-think/transportation/sensors/slight-street-sign-modifications-can-fool-machine-learning-algorithms" target="_blank">this article from IEEE Spectrum</a>, the novelty is that the 'highly efficient attacks' on the ML algorithms are as simple as stickers or grafitti painted in real life traffic signs. Again, those attacks can barely confuse humans, but completely fool ML algorithms<br />
.<br />
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<br />chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-71989768941834696222017-07-30T23:27:00.000+03:002017-07-31T06:30:09.959+03:00Best FPGA development practices - Whitepaper<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg0bvfVYnc6v1N9ymbsoQEedLVbKxlURKc2qShViJYUSETC3tyKZjkuKM-AvKAwW0VNmbL6ObSQWxXjj13Ie4SNQvmgwZ5EbwIAALzgj1Kc7oFie8B6qt8uSUUpQ6w4_VWAqTwD1GRP_A/s1600/reusablecomps1.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" data-original-height="367" data-original-width="386" height="304" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg0bvfVYnc6v1N9ymbsoQEedLVbKxlURKc2qShViJYUSETC3tyKZjkuKM-AvKAwW0VNmbL6ObSQWxXjj13Ie4SNQvmgwZ5EbwIAALzgj1Kc7oFie8B6qt8uSUUpQ6w4_VWAqTwD1GRP_A/s320/reusablecomps1.png" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Reusable blocks (Image source: Altium)</td></tr>
</tbody></table>
<br />
This <a href="http://www.irtc-hq.com/wp-content/uploads/2015/04/Best-FPGA-Development-Practices-2014-02-20.pdf">whitepaper</a> by Charles Fulk and RC Cofer is an excellent summary of several techniques, tools and design guidelines for FPGA:<br />
<br />
<ul>
<li>FPGA design process</li>
<li>Revision control</li>
<li>Coding guidelines</li>
<li>Scripting automation</li>
<li>PCB design for FPGA</li>
<li>VHDL capture and simulation (including OS-VVM package)</li>
<li>Project Management</li>
<li>Design Resources</li>
</ul>
The whitepaper is available <a href="http://www.irtc-hq.com/wp-content/uploads/2015/04/Best-FPGA-Development-Practices-2014-02-20.pdf">here</a>chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-79014333147025906552017-07-29T18:17:00.001+03:002022-09-15T21:21:22.212+03:00Xilinx AXI Stream tutorial - Part 2<div style="text-align: center;">This post is now hosted <a href="https://fpgaer.tech/?p=424">here</a></div><div><br /></div>
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chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com5tag:blogger.com,1999:blog-6368339555743711421.post-8567057793714793982017-07-15T18:19:00.003+03:002022-10-07T18:06:45.123+03:00Xilinx AXI Stream tutorial - Part 1<div class="separator" style="clear: both; text-align: center;">
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Hi,<div><br /><div><p style="background-color: white; box-sizing: inherit; color: #222222; font-family: Lora, serif; font-size: 16px; margin: 0px 0px 24px;">In this series of articles, I am going to present the design of an AXI4-Stream master. As I often do in my tutorials, I will try to show the design procedure for the block, starting from a “bare bones” solution and gradually adding features to it.</p><span id="more-416" style="background-color: white; box-sizing: inherit; color: #222222; font-family: Lora, serif; font-size: 16px;"></span><span style="background-color: white; color: #222222; font-family: Lora, serif; font-size: 16px;"></span><p style="background-color: white; box-sizing: inherit; color: #222222; font-family: Lora, serif; font-size: 16px; margin: 0px 0px 24px;">Xilinx provides a wide range of AXI peripherals/IPs from which to choose. My purpose in making my own block was to learn the protocol ‘hands-on’. As a side effect, this tutorial provides you with a (synthesizable) AXI4 Stream master which I have not seen provided by Xilinx. The closest IP provided by Xilinx, that I know of, is an AXI memory mapped to AXI stream block.</p>
<a href="https://fpgaer.tech/?p=416">Continue reading...</a><br />
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<br /></div></div>chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com1tag:blogger.com,1999:blog-6368339555743711421.post-67078884165822170032017-05-09T20:45:00.000+03:002017-05-09T21:00:06.035+03:00Spartan 7 now available"Xilinx announced today that its Spartan-7 family of FPGAs is now available for order and shipping to standard lead times. As a key member of Xilinx's Cost-Optimized Portfolio, this device family is designed to meet the needs of cost-sensitive markets by delivering low cost and low power entry points that are I/O optimized for connectivity with industry leading performance-per-watt"<br />
<br />
For more information:<br />
<a href="https://www.xilinx.com/news/press/2017/xilinx-spartan-7-fpgas-now-in-production.html">Spartan-7 general availability announcement</a><br />
<a href="https://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html#productTable">Spartan-7 device page</a>chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-81520063701548539282017-05-08T07:04:00.001+03:002017-07-23T00:24:03.660+03:00Match rockets<iframe allowfullscreen="" frameborder="0" height="270" src="https://www.youtube.com/embed/xf0qa0c3Vrw" width="480"></iframe>
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<br />chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-40771141232604399062017-05-07T22:09:00.001+03:002022-09-06T04:29:30.010+03:00Introduction to Verilog<div class="separator" style="clear: both; text-align: left;">This page is now hosted <a href="https://fpgaer.tech/?p=302">here</a></div><br />
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<br />chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-18169148476230216202017-05-07T08:49:00.000+03:002017-05-07T09:04:28.541+03:00DTMF encoding and decodingDual Tone Multi-Frequency (DTMF) is a method for encoding and decoding up to sixteen digits and special characters to be sent over a voice channel.<br />
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DTMF was first developed by Bell Systems in United States, for use in push-button dialing telephones (in constrant to prior phones, which had a mechanic rotary dialing system).<br />
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DTMF is standardized by ITU-T Recommendation <a class="external text" href="http://www.itu.int/rec/T-REC-Q.23/en" rel="nofollow" style="color: #663366; font-family: sans-serif; font-size: 14px; padding-right: 13px; text-decoration-line: none;">Q.23</a><br />
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A DTMF keypad consists of a matrix of sixteen push buttons organized in four rows by four columns. Each button, when pressed, generates a pair of tones. The tones belong to two groups, a low frequency group (697 to 941 Hz) and a high frequency group (1209 to 1633 Hz). On the picture below you can see the buttons and associated frequencies:<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiB6ndqF4I8rpqIZQgrCSks-gy8EVRLHt5t389xcTk6eCAwY6iUSx_cZJSgp9yzEYSLuDoW0TTN8mf_0aYJPfAMTqSz7261yu1BZu5tYgD5Ko5cZZoF7YzhV5H8XrZe1DpmxZ8Yp0jdrw/s1600/dtmf_keypad.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiB6ndqF4I8rpqIZQgrCSks-gy8EVRLHt5t389xcTk6eCAwY6iUSx_cZJSgp9yzEYSLuDoW0TTN8mf_0aYJPfAMTqSz7261yu1BZu5tYgD5Ko5cZZoF7YzhV5H8XrZe1DpmxZ8Yp0jdrw/s1600/dtmf_keypad.png" /></a></div>
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Pressing an '8' generates two tones, one low frequency tone of 852 Hz and one high frequency tone of 1336Hz.<br />
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The frequencies were selected so no one would be an harmonic of another DTMF frequency.<br />
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As it usually is for many digital transmission systems, the encoder is quite simple while the decoder is much more complicated.<br />
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The decoder has to detect the presence of a pair of tones, but it has to filter out wide band signals like speech, which contain the frequencies of all the tones. The decoder must not only detect the presence of a pair of tones, but also the absence of any other pair. Many DTMF decoders also check the absence of the first harmonic of the detected pair of tones, to avoid confusing human voice with a DTMF tones pair.<br />
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Given what was described above, it is obvious that the receiver must make a frequency analysis of the received signal. But an FFT or DFT is a rather expensive algorithm. A preferred alternative is the Goertzel algorithm, which implements a bank of band pass filters in the frequencies of interest (the tone frequencies and, in some cases, their second harmonic).<br />
<br />
I had the idea to publish this series of articles from a discussion on the FPGA projects group in Facebook. For the transmitter, an elegant solution is to use two NCOs to generate the two tones. A more straight forward solution is to use a square wave generator, each square wave belonging to one of the two groups.<br />
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I analyzed the behavior of a Goertzel based decoder on Matlab, for square wave and for sinusoidal tones, and I saw no real loss of detection capabilities for the square wave against the sinusoidal tones. On the following entries of these DTMF series I will explore tone generation using square waves, NCOs... and an intermediate option between the simple square waves and the more complex NCO based solution.<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhyh0-WaHDnOgEHd1U8lgRFyAejvj4lIVpyMtd_aJbZ96bbjKma_LFB_RUYdcd_U6qqWfLGvOKMJVDlZ091bOvTBgbilcjD9NJlE9H8Gh8A0dLRQSJBy2sa1wBR_R0tIq1KIGBevcwaIg/s1600/dtmf_tones.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="235" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhyh0-WaHDnOgEHd1U8lgRFyAejvj4lIVpyMtd_aJbZ96bbjKma_LFB_RUYdcd_U6qqWfLGvOKMJVDlZ091bOvTBgbilcjD9NJlE9H8Gh8A0dLRQSJBy2sa1wBR_R0tIq1KIGBevcwaIg/s640/dtmf_tones.png" width="640" /></a></div>
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In the above figure, a comparison of the Matlab results of decoding sinusoidal tones against square tones. No degradation can be (easily) seen.<br />
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To make a sanity check, I also compared sinusoidal tones against sinusoidal tones with added noise. After adding (a lot of ) noise, it can be seen the degradation of the decoded signal:<br />
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The tone frequencies are still the strongest, but their relative power against those of the other detected frequencies is not so dominant. A threshold based detector would probably report no tones detected under these noise conditions.<br />
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chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-84471523773476221682017-05-06T23:17:00.000+03:002017-05-06T23:17:01.637+03:00Timers block - Part threeIn the <a href="http://fpgasite.blogspot.co.il/2017/04/timers-block.html">first part of this tutorial</a>, we commented about the implementation of a single timer.<br />
The <a href="http://fpgasite.blogspot.co.il/2017/04/timers-block-part-two.html">second part</a> presented the implementation of a register based timers block,<br />
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In this (third) part of the tutorial we will see a different way to implement the timers block. The timers block is a rather thirsty animal, let's see how many resources it needs for several configurations:<br />
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<div>
<center>
<table>
<tbody>
<tr>
</tr>
<tr bgcolor="#BBBBBB">
<th></th>
<th></th>
<th>Quantity of LUT</th>
<th></th>
<th>Quantity of FF</th>
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<tr>
<td>Single 32 bit timer</td>
<td></td>
<td><center>
43</center>
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<td><center>
33</center>
</td>
</tr>
<tr>
</tr>
<tr bgcolor="#DDDDDDD">
<td>16 x 32 bit timers block</td>
<td></td>
<td><center>
704</center>
</td>
<td></td>
<td><center>
528</center>
</td>
</tr>
<tr>
<td>32 x 32 bit timers block</td>
<td></td>
<td><center>
1,408</center>
</td>
<td></td>
<td><center>
1,056</center>
</td>
</tr>
<tr bgcolor="#DDDDDDD">
<td>32 x 64 bit timers block</td>
<td></td>
<td><center>
2,848</center>
</td>
<td></td>
<td><center>
2,080</center>
</td>
</tr>
</tbody>
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</center>
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These numbers can be obtained by changing the <i style="font-weight: bold;">DATA_W </i>and <i style="font-weight: bold;">TIMERS </i>parameters on the VHDL package file and running synthesis for each configuration. After synthesis, in Vivado, we can get the number of used resources by taking a look at "Report utilization".<br />
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A single 32 bit timer takes 33 flip-flops which is quite reasonable. Thirty-two are needed for the timer alone. As the quantity of timers increases (or their width, or both), the quantity of FF used (and of LUTs), increases linearly, which is also quite expected.<br />
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An alternative to this solution is to store the timers in a memory block. The logic for this memory based block is as follows:<br />
<br />
<ol>
<li>If a timer is enabled, retrieve its last value from memory</li>
<li>Decrement the retrieved timer value</li>
<li>Store the updated value back in memory</li>
<li>Repeat steps 1 to 3 for each timer. Once all timers are taken care, start from the first one again.</li>
</ol>
<br />
Additionally, we must take care of timer updates from the host. This can be done in two ways:<br />
<br />
<ol>
<li>Use a dual port memory block, so if the host wants to change the preset of the timer, it can do this anytime. The second port is used by the internal logic of the FPGA implementing the logic that does the steps 1 to 4 </li>
<li>Add an additional step to the four steps list mentioned above. Let's say, step 5. During step 5, if there was any host write, it is taken care of. That is, the setup value for timer 'n' is updated in the memory block with the value written by the host. The implementation that will be presented on the next chapters of this tutorial was done around this last option.</li>
</ol>
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To (hopefully) make the solution more clear, a waveform is attached below presenting the steps done by the timer block controller. As it would be expected, the controller is a state machine:<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjFlaA2_8m8Fkqwy-G-YYrxWTRkORCF3N682paBWP2Xyh10mg_OPVhVAe5yOno4l86pQLxQqzPwJzWwb-ffyKGtEaPta7FqPAkEZfyGZ-ot20bTBWgpC5L_gZk2CBzpad6f231EBnuBoQ/s1600/tblock_timing.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="408" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjFlaA2_8m8Fkqwy-G-YYrxWTRkORCF3N682paBWP2Xyh10mg_OPVhVAe5yOno4l86pQLxQqzPwJzWwb-ffyKGtEaPta7FqPAkEZfyGZ-ot20bTBWgpC5L_gZk2CBzpad6f231EBnuBoQ/s640/tblock_timing.png" width="640" /></a></div>
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<br />
The waveform shows the different states of the machine, and the read-modify-write actions of the controller, as well as the special state used for host access. Notice that while the controller is updating timer 'n', the host can write to timer 'm'. The second write pulse will occur only if there was a host access to update a timer.<br />
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When using the block based solution, the resources used drop sharply: Only 127 LUT and 75 flipflops... and of course, a BRAM block. So, is this the best solution posible?<br />
<br />
As engineers, we know that you almost cannot win on one table without losing on another. If we are winning less usage of LUTs and FFs, chances are that we are losing something else.
What we are losing is <strong><em>paralelism. </em></strong><br />
<br />
Our original timers block works in parallel (each timer register is decremented in parallel and with no connection nor dependency to the operations being performed on other fellow timer registers).
With this new memory-based implementation, we have <em><strong>serialized </strong></em>the operations. We have to read from memory, decrement, and write-back. But not only that, since the memory is accessed sequentially, we must repeat this read-modify-write operation for all the timers.
This fact imposes a limit to the time base of the counters.<br />
<br />
Let's say that our system clock is 50MHz. If we wanted, using the parallel timers, each one could time up to a smallest resolution of 20ns (the inverse of 50MHz).
That is not the case for the memory-based timer block. The lowest possible timing, or resolution, of our timers, is now limited by two factors:
<br />
<br />
<li>The quantity of cycles it take to read-modify-write one timer (4 clock cycles)</li>
<li>The quantity of timers we want to implement (Notice that the width of the timers has no impact, only their quantity).</li>
<div>
<br /></div>
On our case we wanted to implement 32 timers. The maximum achievable resolution for the memory-based timer block is then:
20ns x 4 x 32 = 2,560 ns ~ 2.6us
For most applications this won't be a problem. Most application involving a CPU won't be able to react to changes on that scale, anyway. Many applications will get along happily with timers of 1ms resolution or 0.1ms = 100us, way above the limit we have calculated. <div>
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On the next entry of this series we will comment the code for this new, memory-based solution, as well as its verification. See you soon!
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chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-47235283495472253302017-05-01T18:48:00.002+03:002022-09-03T08:57:55.971+03:00FPGA internal tri-state buses<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjwoea76t4tS1qeUfExVQqpgyI6U8pn6qjg1IyQWmHyJPXo93VivJ4HvSxZDh1SpJAxiF-n528RhruFB-JK3HDyRvHJsdqFq5-Hpr-s8M7vMdurLfbYlXrr0LlMX2CFc0JbOYq-jS8fyg/s1600/bram.png" style="margin-left: auto; margin-right: auto;"><img border="0" height="290" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjwoea76t4tS1qeUfExVQqpgyI6U8pn6qjg1IyQWmHyJPXo93VivJ4HvSxZDh1SpJAxiF-n528RhruFB-JK3HDyRvHJsdqFq5-Hpr-s8M7vMdurLfbYlXrr0LlMX2CFc0JbOYq-jS8fyg/s400/bram.png" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Block RAM memory - Source: Xilinx</td></tr>
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<div class="separator" style="clear: both; text-align: left;">This post is now hosted <a href="https://fpgaer.tech/?p=253">here</a></div>
<br />chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com2tag:blogger.com,1999:blog-6368339555743711421.post-29802464683642757272017-04-28T00:53:00.002+03:002017-04-28T22:40:48.609+03:00The MicroZed chronicles - free FPGA book<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhG2-eCoGz3zQDekLSFxcroKKs733pPbPuH6z0uCcKfYlt6t3R69g5X09Rv3-agiigxpQll-FPLs7XQYXOwzo9A1iI7xzVcDNIqiGK2FyNODFHoDhSGjGpx_ngd7-q9MbfC1OgO4lBf4A/s1600/microzed.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="640" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhG2-eCoGz3zQDekLSFxcroKKs733pPbPuH6z0uCcKfYlt6t3R69g5X09Rv3-agiigxpQll-FPLs7XQYXOwzo9A1iI7xzVcDNIqiGK2FyNODFHoDhSGjGpx_ngd7-q9MbfC1OgO4lBf4A/s640/microzed.png" width="480" /></a></div>
<span style="background-color: white; color: #202020; font-family: "karla" , sans-serif; font-size: 16px;"><br /></span>
<span style="background-color: white; color: #202020; font-family: "karla" , sans-serif; font-size: 16px;">Adam Taylor is the well known author of the MicroZed Chronicles blog on Xilinx website. His Chronicles have been running for several years, and Adam has already compiled entries from his blog in two books. The first book is offered for free on the <a href="https://www.fpgarelated.com/showabstract/18.php#commax_container">FPGARelated </a>website for registered users.</span><br />
<span style="background-color: white; color: #202020; font-family: "karla" , sans-serif; font-size: 16px;"><br /></span>
<span style="color: #202020; font-family: "karla" , sans-serif; font-size: 16px;">This is a partial list of the book contents:</span><br />
<span style="color: #202020; font-family: "karla" , sans-serif; font-size: 16px;"><br /></span>
<br />
<ul style="color: #202020; font-family: Karla, sans-serif; font-size: 16px; list-style-image: initial; list-style-position: initial; margin: 0px 0px 24px 1.25em; padding: 0px;">
<li>Introduction to the Zynq</li>
<li>Software environment and configuration</li>
<li>The Boot loader</li>
<li>XADC</li>
<li>Multiplexed IO</li>
<li>Timers, clocks and watchdogs</li>
<li>Processing System and Programmable Logic</li>
<li>DMA</li>
<li>Adding an Operating System</li>
<li>MultiProcessing</li>
<li>etc.</li>
</ul>
<span style="background-color: white; color: #202020; font-family: "karla" , sans-serif; font-size: 16px;">The book can be find <a href="https://www.fpgarelated.com/showabstract/18.php#commax_container">here</a></span><span style="background-color: white; color: #202020; font-family: "karla" , sans-serif; font-size: 16px;">. Author Adam Taylor is a regular contributor on Xilinx Xcell Daily Blog </span><span style="background-color: white; color: #202020; font-family: "karla" , sans-serif; font-size: 16px;">and he also has his own <a href="http://adiuvoengineering.com/">website</a></span><span style="background-color: white; color: #202020; font-family: "karla" , sans-serif; font-size: 16px;">.</span>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiu9XfzCdYr1OZvmx4rjGK_n8gnALlQYVKsw_gxpxiL5ioUkbZr-mF-JTkXX79BMh37tUV6M8fayNeSSIIqNcpjE-Tc_n8bCMdIZUYvW3D9MSkvHPC_8Uk61nkw7eQ1YvrFiWdmwHwaVA/s1600/fpgaer3.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="258" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiu9XfzCdYr1OZvmx4rjGK_n8gnALlQYVKsw_gxpxiL5ioUkbZr-mF-JTkXX79BMh37tUV6M8fayNeSSIIqNcpjE-Tc_n8bCMdIZUYvW3D9MSkvHPC_8Uk61nkw7eQ1YvrFiWdmwHwaVA/s640/fpgaer3.png" width="640" /></a></div>
chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0tag:blogger.com,1999:blog-6368339555743711421.post-58397578386651197022017-04-26T04:41:00.002+03:002017-04-26T04:48:53.411+03:00Xilinx Announces General Availability of Virtex UltraScale+ FPGAs in Amazon EC2 F1 Instances<table cellpadding="0" cellspacing="0" class="tr-caption-container" style="float: left; margin-right: 1em; text-align: left;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhMORa_9PhzAi0jzV3ufOy1pMmYD5vJ2UoqWCDB5TLPCbYAHtMn9cqMEfT5ouFKVV5o8y2BVYC6LoUHNfKx-lngNuDrzKwOcd7oi20H95MHOediWZF5SJEwIRZaa-_N1PctPdC7xTw6sw/s1600/virtex_u%252B.png" imageanchor="1" style="clear: left; margin-bottom: 1em; margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhMORa_9PhzAi0jzV3ufOy1pMmYD5vJ2UoqWCDB5TLPCbYAHtMn9cqMEfT5ouFKVV5o8y2BVYC6LoUHNfKx-lngNuDrzKwOcd7oi20H95MHOediWZF5SJEwIRZaa-_N1PctPdC7xTw6sw/s1600/virtex_u%252B.png" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Image source: <a href="https://www.xilinx.com/">Xilinx</a></td></tr>
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"Xilinx today announced that its high-performance Xilinx® Virtex® UltraScale+™ FPGAs are available in Amazon Elastic Compute Cloud (Amazon EC2) F1 instances. This instance provides programmable hardware acceleration with FPGAs and enables users to optimize their compute resources for the unique requirements of their workloads...<br />
<br />
... F1 instances will be used to solve complex science, engineering, and business problems that require high bandwidth, enhanced networking, and very high compute capabilities. They are particularly beneficial for applications that are time sensitive such as clinical genomics, financial analytics, video processing, big data, security, and machine learning. "<br />
<span style="background-color: white; font-family: "open sans" , sans-serif; font-size: 14px;"><br /></span>
<br />
<span style="background-color: white; font-family: "open sans" , sans-serif; font-size: 14px;">The Virtex Ultrascale+ family is based on the new </span><span style="background-color: white; font-family: "open sans" , sans-serif; font-size: 14px;">16 nm FinFET+ </span><span style="background-color: white; font-family: "open sans" , sans-serif; font-size: 14px;">technology, and has the following features:</span><br />
<ul>
<li><span style="background-color: white; font-family: "open sans" , sans-serif; font-size: 14px;">Up to 8GB of HBM Gen2 integrated in-package </span></li>
</ul>
<ul>
<li><span style="background-color: white; font-family: "open sans" , sans-serif; font-size: 14px;">Up to 500Mb of on-chip memory integration </span></li>
</ul>
<ul>
<li><span style="background-color: white; font-family: "open sans" , sans-serif; font-size: 14px;">Integrated <a adhocenable="false" href="https://www.xilinx.com/products/intellectual-property/cmac.html" style="background-color: transparent; box-sizing: border-box; color: steelblue; outline: none !important; text-decoration-line: none;">100G Ethernet MAC</a><span style="background-color: transparent;"> with RS-FEC and 150G </span><a adhocenable="false" href="https://www.xilinx.com/products/intellectual-property/interlaken.html" style="background-color: transparent; box-sizing: border-box; color: steelblue; outline: none !important; text-decoration-line: none;">Interlaken</a><span style="background-color: transparent;"> cores</span></span></li>
</ul>
<ul>
<li><span style="background-color: white; font-family: "open sans" , sans-serif; font-size: 14px;">Up to four speed-grade improvement with high utilization</span></li>
</ul>
<ul>
<li><span style="background-color: white; font-family: "open sans" , sans-serif; font-size: 14px;">Up to 128-33G transceivers, deliverin 8.4 Tb of serial bandwidth</span></li>
</ul>
<ul>
<li><span style="background-color: white; font-family: "open sans" , sans-serif; font-size: 14px;">460GB/s HBM bandwidth, and 2,666 Mb/s DDR4 in a mid-speed grade</span></li>
</ul>
<ul>
<li><span style="background-color: white; font-family: "open sans" , sans-serif; font-size: 14px;">Integrated blocks for PCI Express Gen 3x16 and Gen 4x8</span></li>
</ul>
<br />
For more information:<br />
<a href="https://www.xilinx.com/news/press/2017/xilinx-announces-general-availability-of-virtex-ultrascale-fpgas-in-amazon-ec2-f1-instances.html">Original announcement </a>on Xilinx site<br />
About <a href="https://aws.amazon.com/ec2/instance-types/f1/">Amazon EC2 F1 instances</a><br />
About <a href="https://www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale-plus.html">Xilinx Virtex Ultrascale+</a> device family<br />
<br />chclauhttp://www.blogger.com/profile/10299176893102701567noreply@blogger.com0