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This is the third part of a series of articles on VHDL arbiters. In the  first part , we commented on what a VHDL arbiter is. In the  second part , we saw the VHDL code for a fixed-priority VHDL arbiter. When I talked about what a VHDL arbiter is, I gave the example of the single car we have at home, and how I have to decide who gets to use the car next Friday evening. In a typical situation, if both children ask for the car, the first thing they will account for is, who got the car the last time. Continue reading…

In the  first article of this series , we defined what an HW arbiter is. In this entry of the tutorial, we will see a simple implementation of a VHDL arbiter. The arbiter of this example has three request inputs and three grant outputs. It has a fixed priority for the masters. The lower the master number, the higher its priority. The block also has a  busy  signal. Arbitration of the bus is done only while it is inactive. If the bus has already been granted to an agent, even if a bigger priority master requests the bus, the current transaction must complete before the arbiter grants the bus to another master. Continue reading…

Many times I find myself in the need of generating data for testing. We need data for verification, either done on simulation or on the real target. One easy way to test our system is to generate data vectors on RAM. Altera RAM IP includes the ability to initialize RAM contents during power-up by means of a .hex file. One problem of the .hex file format is that it is quite unreadable for humans. Altera came to our rescue with the .mif format, which is text based and very easy to understand. The application I present below initializes a memory (generating an .hex file). The size and width of the memory are parameters. The Matlab application generates both a init_mem.mif and a init_mem.hex file. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 %------------------------------------------- % Generate Parameters ram_size = 256 ; % In words word_size = 16...

What is an arbiter? What is an arbiter? An arbiter is a very common block used on HW designs. I think I can find the best example of an arbiter at home. When my two kids were teenagers, I had only one car. On Friday and Saturday evenings, there was usually a conflict over who got to use the car. Usually, it was on me to decide (arbiter) who got the car. Not an easy task. (I still have only one car. It just happens that my kids are not teenagers anymore, and praise the Lord, they have their own cars). Continue reading...  

Reusable blocks (Image source: Altium) This whitepaper  by Charles Fulk and RC Cofer is an excellent summary of several techniques, tools and design guidelines for FPGA: FPGA design process Revision control Coding guidelines Scripting automation PCB design for FPGA VHDL capture and simulation (including OS-VVM package) Project Management Design Resources The whitepaper is available here

Hi, In this series of articles, I am going to present the design of an AXI4-Stream master. As I often do in my tutorials, I will try to show the design procedure for the block, starting from a “bare bones” solution and gradually adding features to it. Xilinx provides a wide range of AXI peripherals/IPs from which to choose. My purpose in making my own block was to learn the protocol ‘hands-on’. As a side effect, this tutorial provides you with a (synthesizable) AXI4 Stream master which I have not seen provided by Xilinx. The closest IP provided by Xilinx, that I know of, is an AXI memory mapped to AXI stream block. Continue reading...

In the first part of this tutorial , we commented about the implementation of a single timer. The second part presented the implementation of a register based timers block, In this (third) part of the tutorial we will see a different way to implement the timers block. The timers block is a rather thirsty animal, let's see how many resources it needs for several configurations: Quantity of LUT Quantity of FF Single 32 bit timer 43 33 16 x 32 bit timers block 704 528 32 x 32 bit timers block 1,408 1,056 32 x 64 bit timers block 2,848 2,080 These numbers can be obtained by changing the DATA_W and TIMERS parameters on the VHDL package file and running synthesis for each configuration. After synthesis, in Vivado, we can get the number of used resources by taking a look at "Report utilization...

On the following three-part tutorial, a square waveform generator is presented. The requirements for the project are to generate a sequence of square waveforms with different frequencies. For each frequency a number of cycles is generated (different for each one). For each frequency, a distinct duty cycle is also defined. In this implementation the frequency is defined in Hz., and the active high time in ns. The VHDL code does not validate the parameters, i.e, if the active high time for any frequency is longer than its period, the output will be always '1' for that frequency. For each frequency, a number of cycles is defined. This project was born over a discussion in Xilinx forums . Once I did the project for a specific configuration I started thinking about a way to make a generic solution, and this tutorial tries to reflect the design process of this small project. The code is presented below. Three different frequencies FREQ1..3 are defined for this example, 242KHz...

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On the previous entry of this series we went through the VHDL source file and simulation of a Timer component. In this entry, we will instantiate several Timer components to create a timer bank (or block of timers). For this purpose we will instantiate the 'Timer' component presented on the first part of the tutorial several times. The instantiation is done inside a VHDL construct called a FOR GENERATE loop (see lines 50 - 61). The code is attached below: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; use work.top_pack.all ; entity top_timer_blk is port ( clk : in std_logic ; rst : in std_logic ; -- inputs data_in : in std_logic_vector (DATA_W - 1 downto 0 ); -- Data bus, connected to all timers load : ...

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Matlab FFT of LFSR output On the first two chapters  of this Tutorial we started with a simple LFSR module and added a test bench. Then, on  chapters three and four  we upgraded our module with some features and learned to export the test bench data to files. Chapter 5 - Matlab Formal Verification Our VHDL block implements an algorithm that generates pseudo-random numbers. If the register is large enough, the output of the block will have hundreds or thousands of different numbers. How can we be sure that our block is working OK? For algorithms validation, Matlab comes as a very handy tool. First, we will generate an LFSR in Matlab which also creates a results file. Then we can just simply compare both files, if they are equal, we have an additional degree of confidence in our VHDL block. This is what the following Matlab code does: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 % Generate LFSR a = uint32( 0 ); % Order of the polynom, up...

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Do you recognize that feeling when you think you knew something, until somebody asks you to explain it? Well, that was what happened to me when I tried to explain what "Analysis and Elaboration" is. I used it in FPGA tools many times, and I had a certain "knowledge" of what it was, but, what are those processes EXACTLY? And, while we are at it, we will also describe what Synthesis is. Let's see: Analysis Analysis is the process where the design files are checked for syntactic and semantic errors. The syntactic rules are dictated by the language. On VHDL, if you write IF but forget to include the THEN clause, that is a violation of the  syntax , the set of rules of the VHDL language. Semantics are the meaning of the language. A sentence describing an addition is tagged as incorrect if the operands are of incompatible types and the VHDL compiler cannot resolve the meaning of that sentence. Elaboration VHDL designs are hierarchic by natur...

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