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Showing posts with the label Zynq

Guinness - GUI based Neural Network Synthesizer

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Guinness is a GUI based framework that includes both a training on a GPU, and a bitstream generation for an FPGA using the Xilinx SDSoC. This tool uses the Chainer deep learning framework to train a binarized CNN. Also, it uses optimization techniques for an FPGA implementation. Compared with the conventional FPGA realizations, although the classification accuracy is 6.5% decayed, the performance is 2.45 times faster, the power efficiency is slightly better, and the area efficiency is 2.68 times better. Compared with the ARM Cortex-A57, it is 136.8 times faster, it dissipates 3.1 times much power, and its performance per power efficiency is 44.7 times better. Also, compared with the Maxwell embedded GPU, it is 4.9 times faster, it dissipates 1.3 times much power, and its performance per power efficiency is 3.8 times better.  Details are shown in following papers: [Nakahara IPDPSW2017] H. Yonekawa and H. Nakahara, "On-Chip Memory Based Binarized Convolutional Dee...

The MicroZed chronicles - free FPGA book

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Adam Taylor is the well known author of the MicroZed Chronicles blog on Xilinx website. His Chronicles have been running for several years, and Adam has already compiled entries from his blog in two books. The first book is offered for free on the FPGARelated website for registered users. This is a partial list of the book contents: Introduction to the Zynq Software environment and configuration The Boot loader XADC Multiplexed IO Timers, clocks and watchdogs Processing System and Programmable Logic DMA Adding an Operating System MultiProcessing etc. The book can be find here . Author Adam Taylor is a regular contributor on Xilinx Xcell Daily Blog  and he also has his own website .

SoC and MPSoC

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The Zynq book (free)

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