This question gets asked again and again, by beginners and experienced designers alike.
When I saw it posted on the FPGA group at reddit at reddit some time ago, I liked the answer from user fft32, so with his permission, I reproduce it here with some minor changes and additions.
VHDL compared to VerilogVHDL: A bit verbose, clunky syntax. I never liked that different constructs have different rules for the "end" tag, like "end synth" for architectures, versus "end component mux" for components. I always find myself looking up the syntax of packages and functions.Strongly typed: It's a bit of a pain to have to make a (0 downto 0) vector to do something like a carry-in, but at the end of the day, it can save you time debugging problems. You don't scratch your head as to why your 10-bit vector is only 0 to 1, because you assigned a 1-bit value to it (a thing you could do in Verilog, but in VHDL would produce a compile error). Also, by default Verilog…
In this tutorial we will see how to design and test a VHDL component. We will start with a very simple block and gradually add features to it. We will also simulate it and test its output with Matlab. Over the process we will see: How to start with a simple block and gradually add features and improvementsHow to add a test bench (simulation)Adding parameters to a VHDL componentSaving the component data output to files (from simulation)Importing the files to Matlab in order to:Verify the results (Formal testing), andAnalyze the results (in this case, using FFT).The tutorial comprises three chapters, and it is divided into three entries of this blog. Make sure that you haven't missed to visit part 2 and part 3 of the tutorial!
For this tutorial it is assumed that you already have basic knowledge of the VHDL language and know how to use simulation tools (We will use the Xilinx's Vivado built in simulator, but you can easily adapt the tutorial to other tools you may be familiar wi…
This book was published by Xilinx in 2005. While in our very dynamic profession, some of the technologies explained can be a bit outdated, the basic concepts are there for anyone who wishes to learn or refresh his/her concepts about high speed serial links.
Inside the book you will find data about: Serdes transceivers basics8b/10b, 64b/64b encodingClock recoveryLine equalizationChannel BondingSignal IntegrityPower considerationsBoard design considerations, etc.Book Title: High Speed Serial I/O made simple