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Xilinx AXI Stream tutorial - Part 1

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Hi,

In these series of articles I am going to present the design of an AXI4-Stream master. As I often do in my tutorials, I will try to show the design procedure for the block, starting from a "bare bones" solution and gradually adding features to it.

Xilinx provides a wide range of AXI peripherals/IPs from which to choose. My purpose in making my own block was in learning 'hands-on' the protocol. As a side effect, this tutorial provides you with a (synthesizable) AXI4 Stream master which I have not seen provided by Xilinx. The closest IP provided by Xilinx, that I know of, is an AXI memory mapped to AXI stream block.

But first things first, what is AXI4-streaming? Streaming is a way of sending data from one block to another. The idea on streaming devices is to provide a steady flow of high speed data, so usually one new block of data is transferred every clock pulse. Also, to reduce overhead streaming buses do no have addressing. Streaming connections are point to …
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Pseudo random number generator Tutorial

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In this tutorial we will see how to design and test a VHDL component. We will start with a very simple block and gradually add features to it. We will also simulate it and test its output with Matlab. Over the process we will see: How to start with a simple block and gradually add features and improvementsHow to add a test bench (simulation)Adding parameters to a VHDL componentSaving the component data output to files (from simulation)Importing the files to Matlab in order to:Verify the results, andAnalyze the results (in this case, using FFT).The tutorial comprises three chapters, and it is divided into three entries of this blog. Make sure that you haven't missed to visit part 2 and part 3 of the tutorial!
For this tutorial it is assumed that you already have basic knowledge of the VHDL language and know how to use simulation tools (We will use the Xilinx's Vivado built in simulator, but you can easily adapt the tutorial to other tools you may be familiar with).
Chapter 1 - …
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Xilinx AXI Stream tutorial - Part 2

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Hi again,

On the previous chapter of this tutorial we presented the AXI Streaming interface, its main signals and some of its applications.

Now let's go for the funnier stuff, that is, to actually make and test some VHDL code to implement our AXI master. We will proceed gradually, adding features as we go. At the end of this tutorial you will have code that:
Implements an AXI master with variable packet lengthFlow control support (ready and valid)Option for generation of several kinds of data patternsTestbench to check that all features work OKInclude an instantiation of Xilinx's AXI Stream protocol checker IP to verify the correctness of our AXI master core.

So let's see the first version of an AXI master. In this version we will have fixed data length of the packet, and the data will be a progression of ascending numbers (the same counter that controls that the packet length is reached, is used to generate the packet data):


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1…
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