Pseudo random number generator Tutorial
This tutorial is now hosted here
Xilinx AXI Stream tutorial - Part 1
Hi, In this series of articles, I am going to present the design of an AXI4-Stream master. As I often do in my tutorials, I will try to show the design procedure for the block, starting from a “bare bones” solution and gradually adding features to it. Xilinx provides a wide range of AXI peripherals/IPs from which to choose. My purpose in making my own block was to learn the protocol ‘hands-on’. As a side effect, this tutorial provides you with a (synthesizable) AXI4 Stream master which I have not seen provided by Xilinx. The closest IP provided by Xilinx, that I know of, is an AXI memory mapped to AXI stream block. Continue reading...
I have to do a VHDL program:
ReplyDeleteBuild a generator of pseudo-random numbers with the period 15.The polynomial generating this sequence is 1 + v + v ^ 4.The display will be on digit.Use the internal clock of FPGA.
board: basys 3 artix 7
In the examples I did I used XNOR feedback. You may want to read the Wikipedia entry that explains how to generate the polynomial using XOR - https://en.wikipedia.org/wiki/Linear-feedback_shift_register.
DeleteHi - nice blog.
ReplyDeleteJust wanted to add that LFSR are not pseudo random number generators, they are pseudo random bit generators
If you are using them to generate n-bit random numbers you should advance the LFSR 'n' times, to generate n new bits. This avoids the sequence being 'randomly' having n(x+1) = 2*n(x)+1 or n(x+1) = 2*n(x).
Also, because of the way that LFRSs have only 2^n-1 states, (which isn't made clear in the blog) there is a slight bias in the generated bits (which may or may not be significant, depending on your use case.
Hi Mike, thanks!
DeleteThanks also for your insight on how to use the LFSR to produce random numbers instead of bits. I will take this into account to improve the tutorial.
The length is a generated sequence is not 2^n, it is 2^n-1, but only if the polynomial is a generating polynomial. As you can see in your waveform, the signal 'count' never reaches x"F".
ReplyDeleteWhy are you using such a big construct to stop the simulation? 'simend' is a signal, so you can write just "wait until (simend = '1'); assert ....; wait;". Because 'simend' has no other purpose, you could also just wait for the specified time.
Nevertheless, a good testbench should not end with an assertion, you should either terminate all processes (incl. implicit processes like the clock) or use "std.env.stop" to halt the simulation kernel.
Hi Patrick,
DeleteThanks for all the comments you have left. I really appreciate the time you have invested for that. So from your and Mike's inputs I understand I have to make a major upgrade to this tutorial. I hope I will be able to make it soon.
Regards,
Also I have corrected to 2^n-1 as you correctly pointed out.
Delete