tag:blogger.com,1999:blog-6368339555743711421.post7467788567847431469..comments2019-06-17T16:19:33.024+03:00Comments on FPGA Site: Pseudo random number generator TutorialUnknownnoreply@blogger.comBlogger7125tag:blogger.com,1999:blog-6368339555743711421.post-87828271437532960382017-07-30T23:01:03.922+03:002017-07-30T23:01:03.922+03:00Also I have corrected to 2^n-1 as you correctly po...Also I have corrected to 2^n-1 as you correctly pointed out.<br />Claudio Avi Chamihttps://www.blogger.com/profile/10299176893102701567noreply@blogger.comtag:blogger.com,1999:blog-6368339555743711421.post-20844217425941522622017-07-30T21:42:29.053+03:002017-07-30T21:42:29.053+03:00Hi Patrick,
Thanks for all the comments you have ...Hi Patrick,<br /><br />Thanks for all the comments you have left. I really appreciate the time you have invested for that. So from your and Mike's inputs I understand I have to make a major upgrade to this tutorial. I hope I will be able to make it soon.<br /><br />Regards,Claudio Avi Chamihttps://www.blogger.com/profile/10299176893102701567noreply@blogger.comtag:blogger.com,1999:blog-6368339555743711421.post-32213421825354831382017-07-30T21:40:05.546+03:002017-07-30T21:40:05.546+03:00Hi Mike, thanks!
Thanks also for your insight on ...Hi Mike, thanks!<br /><br />Thanks also for your insight on how to use the LFSR to produce random numbers instead of bits. I will take this into account to improve the tutorial.Claudio Avi Chamihttps://www.blogger.com/profile/10299176893102701567noreply@blogger.comtag:blogger.com,1999:blog-6368339555743711421.post-12939666739001867512017-07-30T15:27:06.273+03:002017-07-30T15:27:06.273+03:00The length is a generated sequence is not 2^n, it ...The length is a generated sequence is not 2^n, it is 2^n-1, but only if the polynomial is a generating polynomial. As you can see in your waveform, the signal 'count' never reaches x"F".<br /><br />Why are you using such a big construct to stop the simulation? 'simend' is a signal, so you can write just "wait until (simend = '1'); assert ....; wait;". Because 'simend' has no other purpose, you could also just wait for the specified time.<br /><br />Nevertheless, a good testbench should not end with an assertion, you should either terminate all processes (incl. implicit processes like the clock) or use "std.env.stop" to halt the simulation kernel.Patrick Lehmannhttps://www.blogger.com/profile/14729050881797829046noreply@blogger.comtag:blogger.com,1999:blog-6368339555743711421.post-55138187276829942472017-07-30T11:24:26.159+03:002017-07-30T11:24:26.159+03:00Hi - nice blog.
Just wanted to add that LFSR are ...Hi - nice blog.<br /><br />Just wanted to add that LFSR are not pseudo random number generators, they are pseudo random bit generators<br /><br />If you are using them to generate n-bit random numbers you should advance the LFSR 'n' times, to generate n new bits. This avoids the sequence being 'randomly' having n(x+1) = 2*n(x)+1 or n(x+1) = 2*n(x).<br /><br />Also, because of the way that LFRSs have only 2^n-1 states, (which isn't made clear in the blog) there is a slight bias in the generated bits (which may or may not be significant, depending on your use case.Mike Fieldhttps://www.blogger.com/profile/08770196874860581196noreply@blogger.comtag:blogger.com,1999:blog-6368339555743711421.post-77757875134993118742017-05-09T07:36:22.981+03:002017-05-09T07:36:22.981+03:00In the examples I did I used XNOR feedback. You ma...In the examples I did I used XNOR feedback. You may want to read the Wikipedia entry that explains how to generate the polynomial using XOR - https://en.wikipedia.org/wiki/Linear-feedback_shift_register. Claudio Avi Chamihttps://www.blogger.com/profile/10299176893102701567noreply@blogger.comtag:blogger.com,1999:blog-6368339555743711421.post-81812033249242864872017-05-09T00:26:49.511+03:002017-05-09T00:26:49.511+03:00I have to do a VHDL program:
Build a generator ...I have to do a VHDL program: <br /><br /> Build a generator of pseudo-random numbers with the period 15.The polynomial generating this sequence is 1 + v + v ^ 4.The display will be on digit.Use the internal clock of FPGA.<br /><br />board: basys 3 artix 7Cosmin Chttps://www.blogger.com/profile/06732962878467853355noreply@blogger.com