Prototypical – FPGA prototyping free book

This article is now hosted here

Comments

Post a Comment

Popular posts from this blog

Xilinx AXI Stream tutorial - Part 1

Image
Hi, In this series of articles, I am going to present the design of an AXI4-Stream master. As I often do in my tutorials, I will try to show the design procedure for the block, starting from a “bare bones” solution and gradually adding features to it. Xilinx provides a wide range of AXI peripherals/IPs from which to choose. My purpose in making my own block was to learn the protocol ‘hands-on’. As a side effect, this tutorial provides you with a (synthesizable) AXI4 Stream master which I have not seen provided by Xilinx. The closest IP provided by Xilinx, that I know of, is an AXI memory mapped to AXI stream block. Continue reading...
Keep reading

Analysis, elaboration and synthesis

Image
Do you recognize that feeling when you think you knew something, until somebody asks you to explain it? Well, that was what happened to me when I tried to explain what "Analysis and Elaboration" is. I used it in FPGA tools many times, and I had a certain "knowledge" of what it was, but, what are those processes EXACTLY? And, while we are at it, we will also describe what Synthesis is. Let's see: Analysis Analysis is the process where the design files are checked for syntactic and semantic errors. The syntactic rules are dictated by the language. On VHDL, if you write IF but forget to include the THEN clause, that is a violation of the  syntax , the set of rules of the VHDL language. Semantics are the meaning of the language. A sentence describing an addition is tagged as incorrect if the operands are of incompatible types and the VHDL compiler cannot resolve the meaning of that sentence. Elaboration VHDL designs are hierarchic by natur
Keep reading