Innovate FPGA contest

A global FPGA design contest held by Intel and Terasic, starting tomorrow! All FPGA developers can join the contest as teams and compete or join as a community member and vote! "The Innovate Asia, Nordic, and North America contests have inspired thousands of aspiring engineers to design, create, and innovate. This year, these regional events have been combined into a single global contest – Innovate FPGA – where teams from around the world compete as they invent the future of embedded compute with Terasic and Intel. The competition is open to everyone including students, professors, makers, and industry. Teams can showcase their creativity and innovation with actual results and real-world designs. Eligible teams will receive a FREE DE10-Nano development kit!"

Understanding Machine Learning - free book

Machine learning is one of the fastest growing areas of computer science, with far-reaching applications. The aim of the textbook is to introduce machine learning, and the algorithmic paradigms it offers, in a principled way.

The book, "Understanding Machine Learning: From theory to Algorithms", provides a theoretical account of the fundamentals underlying machine learning and the mathematical derivations that transform these principles into practical algorithms. Following a presentation of the basics, the book covers a wide array of central topics unaddressed by previous textbooks. These include a discussion of the computational complexity of learning and the concepts of convexity and stability; important algorithmic paradigms including stochastic gradient descent, neural networks, and structured output learning; and emerging theoretical concepts such as the PAC-Bayes approach and compression-based bounds.

Designed for advanced undergraduates or beginning graduates, the te…

Organizing your tasks, and design files

Men marry women wishing they will never change, but they do.
Women marry men wishing they will be able to change them, but they don't.
When I was young, even during my University studies, I was a real disaster in anything related to order and tidiness. My room was always a mess. Whenever my mother or any other would try to change my ways (even a little bit), I would say what many like me love to say: - "In the disorder, I know where everything is. When my mother makes some order, I can't find anything".

And to demonstrate that the half-joke at the beginning of this article is not true, I must say that I changed a lot since I married. My home won't appear in a decoration magazine, but it is not close at all to my young-days' complete-mess room.

The other reason I have to train me all the time to be a more tidy person is that I work in FPGA design. So if you are rolling your eyes thinking that order has nothing to do with design, and I'd better publish some …

Giant Hovercrafts - past and future


Can AI be Conscious?

by Bernard Murphy (*)

I found a recent Wired article based on a TED talk on consciousness. The speaker drew a conclusion that consciousness was not something that could ever be captured in a machine and was a unique capability of living creatures (or at least humans). After reading an article on the the TED talk and watching a related talk, I’m not so sure but I am fairly convinced that whatever we might build in this direction may be quite different from our consciousness, will probably take a long time and will be plagued with problems.

The TED event (speaker Anil Seth, Professor of neuroscience at the University of Essex in the UK) is not posted yet, but there is a more detailed talk by the same speaker on the same topic, given recently at the Royal Institute, which I used as a reference.

First, my own observations (not drawn from the talk). AI today is task-based, in each case skilled at doing one thing. That thing might be impressive, like playing Go or Jeopardy, providing tax advi…

VHDL arbiters - part II

This tutorial was designed using Quartus and Modelsim-Altera

In the previous installment, we defined what a HW arbiter is.
In this entry of the tutorial, we will see a simple implementation of a VHDL arbiter.

The arbiter of this example has three request inputs and three grant outputs.
Additionally, it has a 'busy' signal. Arbitration of the bus is done only while it is inactive. If the bus has already been granted to an agent, even if a bigger priority master requests the bus, the current transaction must complete before the arbiter gives grant signal to another master.

The logic for generating the grant signals (lines 41-43) is quite simple. If the first master (master 0) asserts a request, it is awarded grant. Master 1 is given grant only if it requests the bus and master 0 doesn't request the bus.
Master 2 is awarded grant only if it requests the bus and neither master 0 nor master 1 request the bus.

The gnt signal is changes only if the bus is not busy. The process an…