Showing posts from May, 2017

Spartan 7 now available

"Xilinx announced today that its Spartan-7 family of FPGAs is now available for order and shipping to standard lead times. As a key member of Xilinx's Cost-Optimized Portfolio, this device family is designed to meet the needs of cost-sensitive markets by delivering low cost and low power entry points that are I/O optimized for connectivity with industry leading performance-per-watt"

For more information:
Spartan-7 general availability announcement
Spartan-7 device page

Match rockets


Introduction to Verilog

This blog motto is FPGA projects in VHDL. It also includes free VHDL books. But, in a past comment on Hacker News I saw this nice Verilog short guide and I knew I have to share it here.

Besides, the FPGA world is evolving. In my experience, it is not enough to know one manufacturer. You may need more. Nor it is enough to know only VHDL. You'd better know also Verilog. And even start thinking to learn other resources and tools, like HLS.

So, now that I have finished (more or less) for publishing this link, here it is

The short, 32 page guide includes the following subjects:

Gate-Level ModellingData TypesOperatorsOperandsModulesBehavioral ModelingFunctionsComponent InferenceFinite State MachinesCompiler DirectivesSystem Tasks and FunctionsTest Benches, andMemories This short and useful Introduction to Verilog is published by Carleton University 

DTMF encoding and decoding

Dual Tone Multi-Frequency (DTMF) is a method for encoding and decoding up to sixteen digits and special characters to be sent over a voice channel.

DTMF was first developed by Bell Systems in United States, for use in push-button dialing telephones (in constrant to prior phones, which had a mechanic rotary dialing system).

DTMF is standardized by ITU-T Recommendation Q.23

A DTMF keypad consists of a matrix of sixteen push buttons organized in four rows by four columns. Each button, when pressed, generates a pair of tones. The tones belong to two groups, a low frequency group (697 to 941 Hz) and a high frequency group (1209 to 1633 Hz). On the picture below you can see the buttons and associated frequencies:

Pressing an '8' generates two tones, one low frequency tone of 852 Hz and one high frequency tone of 1336Hz.

The frequencies were selected so no one would be an harmonic of another DTMF frequency.

As it usually is for many digital transmission systems, the encoder is quite …

Timers block - Part three

In the first part of this tutorial, we commented about the implementation of a single timer.
The second part presented the implementation of a register based timers block,

In this (third) part of the tutorial we will see a different way to implement the timers block. The timers block is a rather thirsty animal, let's see how many resources it needs for several configurations:

Quantity of LUTQuantity of FFSingle 32 bit timer 43 3316 x 32 bit timers block 704 52832 x 32 bit timers block 1,408 1,05632 x 64 bit timers block 2,848 2,080

These numbers can be obtained by changing the DATA_W and TIMERS parameters on the VHDL package file and running synthesis for each configuration. After synthesis, in Vivado, we can get the number of used resources by taking a look at "Report utilization".

A single 32 bit timer takes 33 flip-flops which is quite reasonable. Thirty-two are needed for the timer alone. As the quantity of timers increases (or their width, or both), the quantity of F…

FPGA internal tri-state buses

For many designers, the first time we saw the internal memory blocks in an FPGA came as a little shock.

Some of us were used to RAM devices used in Board Design. These devices use bidirectional data buses. Even the fastest memories, DDRn DRAMs, use bidirectional data buses ('n' has changed over the years, from plain DDR to current DDR4).

So, how comes that internal memories on an FPGA have TWO data buses? Isn't that a waste of resources? Why don't FPGAs have internal tri-state buses?

Well, until around fifteen years ago, some FPGA devices DID have internal tri-state buffers. With the evolution of semiconductors technology, internal tri-state buffers were abandoned. So today, FPGAs don't have tri-state buffers but have unidirectional buses only. Since most memories are readable and writable, two unidirectional data buses are needed between a controller (CPU, internal FPGA logic) and the memory.

If this answer is enough for you, you can stop reading here. If you wan…