Showing posts from 2017

Innovate FPGA contest

A global FPGA design contest held by Intel and Terasic, starting tomorrow! All FPGA developers can join the contest as teams and compete or join as a community member and vote! "The Innovate Asia, Nordic, and North America contests have inspired thousands of aspiring engineers to design, create, and innovate. This year, these regional events have been combined into a single global contest – Innovate FPGA – where teams from around the world compete as they invent the future of embedded compute with Terasic and Intel. The competition is open to everyone including students, professors, makers, and industry. Teams can showcase their creativity and innovation with actual results and real-world designs. Eligible teams will receive a FREE DE10-Nano development kit!"

Understanding Machine Learning - free book

Machine learning is one of the fastest growing areas of computer science, with far-reaching applications. The aim of the textbook is to introduce machine learning, and the algorithmic paradigms it offers, in a principled way.

The book, "Understanding Machine Learning: From theory to Algorithms", provides a theoretical account of the fundamentals underlying machine learning and the mathematical derivations that transform these principles into practical algorithms. Following a presentation of the basics, the book covers a wide array of central topics unaddressed by previous textbooks. These include a discussion of the computational complexity of learning and the concepts of convexity and stability; important algorithmic paradigms including stochastic gradient descent, neural networks, and structured output learning; and emerging theoretical concepts such as the PAC-Bayes approach and compression-based bounds.

Designed for advanced undergraduates or beginning graduates, the te…

Organizing your tasks, and design files

Men marry women wishing they will never change, but they do.
Women marry men wishing they will be able to change them, but they don't.
When I was young, even during my University studies, I was a real disaster in anything related to order and tidiness. My room was always a mess. Whenever my mother or any other would try to change my ways (even a little bit), I would say what many like me love to say: - "In the disorder, I know where everything is. When my mother makes some order, I can't find anything".

And to demonstrate that the half-joke at the beginning of this article is not true, I must say that I changed a lot since I married. My home won't appear in a decoration magazine, but it is not close at all to my young-days' complete-mess room.

The other reason I have to train me all the time to be a more tidy person is that I work in FPGA design. So if you are rolling your eyes thinking that order has nothing to do with design, and I'd better publish some …

Giant Hovercrafts - past and future


Can AI be Conscious?

by Bernard Murphy (*)

I found a recent Wired article based on a TED talk on consciousness. The speaker drew a conclusion that consciousness was not something that could ever be captured in a machine and was a unique capability of living creatures (or at least humans). After reading an article on the the TED talk and watching a related talk, I’m not so sure but I am fairly convinced that whatever we might build in this direction may be quite different from our consciousness, will probably take a long time and will be plagued with problems.

The TED event (speaker Anil Seth, Professor of neuroscience at the University of Essex in the UK) is not posted yet, but there is a more detailed talk by the same speaker on the same topic, given recently at the Royal Institute, which I used as a reference.

First, my own observations (not drawn from the talk). AI today is task-based, in each case skilled at doing one thing. That thing might be impressive, like playing Go or Jeopardy, providing tax advi…

VHDL arbiters - part II

This tutorial was designed using Quartus and Modelsim-Altera

In the previous installment, we defined what a HW arbiter is.
In this entry of the tutorial, we will see a simple implementation of a VHDL arbiter.

The arbiter of this example has three request inputs and three grant outputs.
Additionally, it has a 'busy' signal. Arbitration of the bus is done only while it is inactive. If the bus has already been granted to an agent, even if a bigger priority master requests the bus, the current transaction must complete before the arbiter gives grant signal to another master.

The logic for generating the grant signals (lines 41-43) is quite simple. If the first master (master 0) asserts a request, it is awarded grant. Master 1 is given grant only if it requests the bus and master 0 doesn't request the bus.
Master 2 is awarded grant only if it requests the bus and neither master 0 nor master 1 request the bus.

The gnt signal is changes only if the bus is not busy. The process an…

FPGA for dummies - free book

If you are completely new to FPGAs, or if you want a refreshing high level view of what FPGAs are and what are the future trends in the field, you can download this free book from Altera site:

FPGA for dummies

The book is an all-text introduction to this exciting field, do not expect to find real examples nor VHDL code in the book.

MIF_Gen - A Matlab Utility

Many times I find myself in the need of generating data for testing. We need data for verification, either done on simulation or on the real target.

One easy way to test our system is to generate data vectors on RAM. Altera RAM IP includes the ability to initialize RAM contents during power-up by means of a .hex file.
One problem of the .hex file format is that it is quite unreadable for humans. Altera came to our rescue with the .mif format, which is text based and very easy to understand.

The application I present below initializes a memory (generating an .hex file). The size and width of the memory are parameters. The Matlab application generates both a init_mem.mif and a init_mem.hex file.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52%-------------------------------------------% Generate Parameters ram_size = 256; % In words word_size = 16; % Can be 8, 16, …

VHDL arbiters

What is an arbiter? An arbiter is a very common block used on HW designs.

I think I can find the best example of an arbiter at home. I have only one car, and two young kids, both of them with their own driving licenses. On Friday and Saturday evenings, there will be usually a conflict over who gets to use the car. Usually it falls on me to arbiter who gets the car. Not an easy task.

HW boards are not that different. There are at least two cases where a common (and valued, and expensive) resource is 'wanted' by several users:
Common memory: It is very usual to see boards where fast memory (i.e. DDR) is shared between a processor and an FPGA. Obviously a memory cannot answer to two masters at once. The processor, and the FPGA, ask the arbiter for permission to access the memory. Even if it is done at very high speed and simultaneously for our perception, in reality the FPGA and the processor have to take turns to own the memory. NOTE: There are other applications where even more…

Functional Safety Primer for FPGA White Paper

by Bernard Murphy (*)

Following up on their webinar on functional safety in FPGA-based designs, Synopsys have now published a white paper expanding on some of those topics. For those who didn’t get a chance to see the webinar this blog follows the white paper flow and is similar but not identical to my webinar blog, particularly around differences between different FPGA architectures. The topic is design for functional safety, particularly as applied to FPGA design and how these techniques can be implemented using Synopsys’ Synplify Premier. In fact, in this very detailed review I saw little that isn’t of equal relevance in ASIC design, though typically implemented using different tools and methodologies.
The paper kicks off with a bite-sized summary of the IEC 61508 standard for safety in industrial electrical and electronic systems and the ever-popular ISO 26262 standard for safety in automotive electronic systems. Both are useful to have on hand when someone asks you what you kn…

FPGAs and Deep Machine Learning

The concept of machine learning is not new. Attempts at systems emulating intelligent behavior, like expert systems, go as far back as the early 1980's. And the very notion of modern Artificial Intelligence has a long history. The name itself was coined at a Dartmouth College conference (1956), but the idea of an "electronic brain" was born together with the development of modern computers. AI as an idea accompanies us from the dawn of human history.
Three latest development are pushing forward "Machine Learning":
Powerful distributed processorsCheap and high volume storageHigh bandwidth interconnection to bring the data to the processors As in many other fields, development of Machine Learning is also seeing development on algorithms that take advantage of the new hardware capabilities.
There are four types of algorithms used in machine learning:
Supervised - The vast majority of systems today. These systems are 'trained' based on past data on an attemp…

Guinness - GUI based Neural Network Synthesizer

Guinness is a GUI based framework that includes both a training on a GPU, and a bitstream generation for an FPGA using the Xilinx SDSoC. This tool uses the Chainer deep learning framework to train a binarized CNN. Also, it uses optimization techniques for an FPGA implementation.
Compared with the conventional FPGA realizations, although the classification accuracy is 6.5% decayed, the performance is 2.45 times faster, the power efficiency is slightly better, and the area efficiency is 2.68 times better. Compared with the ARM Cortex-A57, it is 136.8 times faster, it dissipates 3.1 times much power, and its performance per power efficiency is 44.7 times better. Also, compared with the Maxwell embedded GPU, it is 4.9 times faster, it dissipates 1.3 times much power, and its performance per power efficiency is 3.8 times better. 
Details are shown in following papers:
[Nakahara IPDPSW2017] H. Yonekawa and H. Nakahara, "On-Chip Memory Based Binarized Convolutional Deep Neural Network Appl…

Machine Learning Optimizes FPGA Timing

By Bernard Murphy (*)

Machine learning (ML) is the hot new technology of our time so EDA development teams are eagerly searching for new ways to optimize various facets of design using ML to distill wisdom from the mountains of data generated in previous designs. Pre-ML, we had little interest in historical data and would mostly look only at localized comparisons with recent runs to decide whatever we felt were best-case implementations. Now, prompted by demonstrated ML-value in other domains, we are starting to look for hidden intelligence in a broader range of data.

One such direction uses machine-learning methods to find a path to optimization. Plunify does this with their InTime optimizer for FPGA design. The tool operates as a plugin to a variety of standard FPGA design tools but does the clever part in the cloud (private or public at your choice), in which the goal is to provide optimized strategies for synthesis and place and route.

There is a very limited way to do this toda…


FPGAs and GPUs: a Tour of SETI's Computer Hardware

David MacMahon is a research astronomer with Berkeley SETI Research Center. Dave works on several projects at BSRC, including Breakthrough Listen, designing many of the computer systems we use to process data collected from our telescopes. If you've ever been curious what hardware is required to search for ET, check out this tour of Berkeley SETI behind the scenes.

Slight Street Sign Modifications Can Completely Fool Machine Learning Algorithms

Machine Learning is a hot I+D topic.

One of the strategies used in Machine Learning is to learn by means of neural networks. You can get a free introduction to neural networks here.
I also warmly recommend Andrew Ng's introductory course to Machine Learning on Coursera.

Machine Learning neural networks were inspired by biological neural networks, and are easily applied but highly effective in image processing algorithms, like handwritten text recognition.

More complex neural networks algorithms are being implemented on what is called Deep Machine Learning, using neural networks with many layers of complexity.

Typically a neural network is trained, or it learns, from its exposure to thousands of 'good' and 'bad' examples of the image to be recognized or classfied. For example, a neural network that has to recognize handwritten numbers, will be exposed to thousands of examples of numbers written by different people, and even with changes in the orientation of the te…

Best FPGA development practices - Whitepaper

This whitepaper by Charles Fulk and RC Cofer is an excellent summary of several techniques, tools and design guidelines for FPGA:

FPGA design processRevision controlCoding guidelinesScripting automationPCB design for FPGAVHDL capture and simulation (including OS-VVM package)Project ManagementDesign Resources The whitepaper is available here

Xilinx AXI Stream tutorial - Part 2

Hi again,

On the previous chapter of this tutorial we presented the AXI Streaming interface, its main signals and some of its applications.

Now let's go for the funnier stuff, that is, to actually make and test some VHDL code to implement our AXI master. We will proceed gradually, adding features as we go. At the end of this tutorial you will have code that:
Implements an AXI master with variable packet lengthFlow control support (ready and valid)Option for generation of several kinds of data patternsTestbench to check that all features work OKInclude an instantiation of Xilinx's AXI Stream protocol checker IP to verify the correctness of our AXI master core.

So let's see the first version of an AXI master. In this version we will have fixed data length of the packet, and the data will be a progression of ascending numbers (the same counter that controls that the packet length is reached, is used to generate the packet data):

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1…