VHDL or Verilog?

This question gets asked again and again, by beginners and experienced designers alike.
When I saw it posted on the FPGA group at reddit at reddit some time ago, I liked the answer from user fft32, so with his permission, I reproduce it here with some minor changes and additions.

VHDL compared to Verilog

  • A bit verbose, clunky syntax. I never liked that different constructs have different rules for the "end" tag, like "end synth" for architectures, versus "end component mux" for components. I always find myself looking up the syntax of packages and functions.
  • Strongly typed: It's a bit of a pain to have to make a (0 downto 0) vector to do something like a carry-in, but at the end of the day, it can save you time debugging problems. You don't scratch your head as to why your 10-bit vector is only 0 to 1, because you assigned a 1-bit value to it (a thing you could do in Verilog, but in VHDL would produce a compile error). Also, by default Verilog undeclared signals default to 1-bit nets. Once I acciddentaly did this with a clock and I was wondering why nothing worked.
  • Libraries: This is good and bad for me. It's great to wrap your code in an organized and reusable manner. However, many "everyday" functions come from libraries rather than built into the language. There are non-standard libraries like std_logic_unsigned/std_logic_signed that are used in a lot of legacy code and old code examples. They've since been replaced by numeric_std. The conversion between types needs functions whose format is quite annoying.

  • Writing code seems more streamlined. No component declarations, loose data types (everything is just bits, really).
  • C-like syntax.
  • Resulting code is more compact.
  • Low-level descriptions are closer to actual hardware.
  • Verilog has a poor design of its concurrency resolution scheme. Being an HDL, concurrency is obviously a very important aspect. Here is a write up concerning this point.
At the end of the day, the two languages are really able to achieve the same designs. I think it's good to understand code in both languages, but since mixed language support is common, I don't see an issue sticking with the one that you prefer.
To the comments from fft32, I would add that in my opinion, Verilog with its plain syntax is easier to learn and grasp for the beginner.
Also, from my experience, Verilog tends to be dominant in the ASIC arena, while VHDL is the language of choice for most FPGA designs.

?And the winner is

Well, none of the two, at least as these words are written. In the long run, as you advance in your HDL designer career, you will be probably using both, although also probably using one of them most of the time.
If you are wondering which one you should start with, take the one that you feel more comfortable with. Or, ask colleagues and teachers which one is most needed in the market niche you want to be part of. The important thing is to grasp the structures behind the language, and not the language itself.
To be honest, it seems that both fft32 and me mostly used VHDL, so this comparison could be a little biased. But, after all, both languages are Hardware Description Languages. So what really matters are the flip-flops and gates that give life to your design, and not so much how in what language you describe them.
Whatever you choose, good luck!


On May 2017 I put a link about this blog topic in Hacker News. For some reason, the link got a lot of hits and there also was a lively interchange of comments regarding Verilog, VHDL... and the future of HDL languages. 

I have summarized some of the comments below:
  1. It seems that Verilog got its syntax from C, and VHDL from Ada. I don't know Ada so I couldn't tell, but Verilog looks C'ish to me also.
  2. System Verilog is also a language worth checking, since it has powerful verification constructs.
  3. Many people talked about what seems to be the next step, which could leave VHDL and Verilog behind (as C left Assembler behind, might I add). The next step is called High Level Synthesis and the two major FPGA manufacturers are supporting it: OpenCL from Altera and HLS from Xilinx.
  4. Other HLS suppliers mentioned: Chysel and MyHDL with Python
  5. And last, for the lighter side of the issue, some time ago there was a competition between VHDL and Verilog... For more details, check here (actually this is very old, and I don't think its results are conclusive, but I thought I would be fun to mention it).
If you want to check all the comments on Hacker News by yourself, here they are.


  1. What about licences issues and available free softwares ?

    1. Hi,
      Thanks for your question. It is a really big one. License covers several aspects, for example, one aspect of the license is wether you can synthesize Verilog or VHDL. Another aspect is your capabilities to simulate. And yet another one, is if mixed languages designs are supported. As a general answer, both major FPGA providers, Intel Altera and Xilinx, provide some form of free access to tools. This free access changes from time to time regarding what features are delivered and which devices are covered. You'd better check in their websites.

    2. Verilog has Verilator and Icarus Verilog, whereas VHDL has NVC and GHDL as free simulators. Generated waveforms can be viewed in GTKwave. With YOSYS, a first free synthesis tool is available for Lattice iCE 40 FPGAs. YOSYS consumes Verilog code by default, but the GHDL project is working on a proof-of-concept for a VHDL frontend for YOSYS.

  2. MyHDL is not a HLS language. It's HDL in the same RTL level as VHDL/Verilog. The power it brings is related to have a very clear language as basis: Python. Also it really has far devanced testing support from Python core libraries.

  3. Unfortunately the comparison misses some important features of VHDL, which do not exist in Verilog and were added in SystemVerilog: This includes Enumeration Types (make Code extremely well readable), Records (can be used to dramatically simplify transaction level interfaces), Assert statements (extremly helpful in debugging).
    Language style for me is secondary. I come from Pascal and therefore prefer the syntax style of VHDL (rather text than symbols), a C programmer may prefer the Verilog look-alike. The additional testbench oriented features of SV require a good understanding of OOP which unfortunately not all HDL designers have..
    And about syntax "problems": there are so many language sensitive (free) editors available, that syntax details is definitely no topic anymore!
    But as the text says: Both VHDL and Verilog (and also SV) are HDL and at the end you can do all with both languages.

  4. If you are going to bother to do a review, include the latest information - like with VHDL-2008 VHDL is as concise as Verilog or SystemVerilog and with the OSVVM verification library that VHDL is as capable and concise as SystemVerilog + UVM.

  5. We may as well debate Emacs vs. Vi while we're at it :). Both are equally obsolete. Si has evolved to incorporate 25000x(!) more transistors over the lifetime of these languages. The problem is there's been nothing palatable to replace them with. Modeling hardware w/ C++ is absurd. Chisel is interesting, but rather scary to most designers. Fortunately, there's a newcomer -- Transaction-Level Verilog (TL-Verilog) that introduces abstract design constructs without giving up on RTL details. You really need to check it out. It has clean syntax that's easy to learn. I lead the development of makerchip.com where you can learn about and develop in TL-Verilog. Certainly I'm biased, but I assure you, you will never look back to RTL languages again!


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