Analysis, elaboration and synthesis

Do you recognize that feeling when you think you knew something, until somebody asks you to explain it?
Well, that was what happened to me when I tried to explain what "Analysis and Elaboration" is. I used it in FPGA tools many times, and I had a certain "knowledge" of what it was, but, what are those processes EXACTLY? And, while we are at it, we will also describe what Synthesis is.
Let's see:


Analysis is the process where the design files are checked for syntactic and semantic errors. The syntactic rules are dictated by the language. On VHDL, if you write IF but forget to include the THEN clause, that is a violation of the syntax, the set of rules of the VHDL language.
Semantics are the meaning of the language. A sentence describing an addition is tagged as incorrect if the operands are of incompatible types and the VHDL compiler cannot resolve the meaning of that sentence.


VHDL designs are hierarchic by nature. The top entity instantiates signals, components and processes. Each component instantiates additional signals, components and processes. The compiler explores the top-down design hierarchy and builds an interconnection table until it reaches the building blocks of the design. At this step the building blocks are still generic RTL constructs: Logic gates, registers, memories, etc. 


During Synthesis, the design is mapped from RTL generic constructs to gate-level components. On an FPGA the building blocks are the device primitives: LUTs, flip-flops, memories, PLLs, input-output pins, etc.


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