FPGA Site

FPGASite is alive and kicking! (We just changed our website address). The new blog has several new articles and features, in addition to actualizations of articles that were hosted in the past on this website. Examples: A series of  articles and projects for Digilent’s Basys 3 board (using an Artix-7 FPGA from Xilinx) New technical articles and code snippets , among them: AXI-Lite registers bank Xilinx AXI Chip2Chip for multi-FPGA designs … and many more! And a selection of legally free books on FPGAs, VHDL, Machine Learning, Verification, etc. See you there, at the new  FPGA'er website :

Add captio A global FPGA design contest held by Intel and Terasic, starting tomorrow! All FPGA developers can join the contest as teams and compete or join as a community member and vote! "The Innovate Asia, Nordic, and North America contests have inspired thousands of aspiring engineers to design, create, and innovate. This year, these regional events have been combined into a single global contest – Innovate FPGA – where teams from around the world compete as they invent the future of embedded compute with Terasic and Intel. The competition is open to everyone including students, professors, makers, and industry. Teams can showcase their creativity and innovation with actual results and real-world designs. Eligible teams will receive a FREE DE10-Nano development kit!"

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Men marry women wishing they will never change, but they do. Women marry men wishing they will be able to change them, but they don't. When I was young, even during my University studies, I was a real disaster in anything related to order and tidiness. My room was always a mess. Whenever my mother or any other would try to change my ways (even a little bit), I would say what many like me love to say: - "In the disorder, I know where everything is. When my mother makes some order, I can't find anything". And to demonstrate that the half-joke at the beginning of this article is not true, I must say that I changed a lot since I married. My home won't appear in a decoration magazine, but it is not close at all to my young-days' complete-mess room. The other reason I have to train me all the time to be a more tidy person is that I work in FPGA design. So if you are rolling your eyes thinking that order has nothing to do with design, and I'd better publi...

In the  first article of this series , we defined what an HW arbiter is. In this entry of the tutorial, we will see a simple implementation of a VHDL arbiter. The arbiter of this example has three request inputs and three grant outputs. It has a fixed priority for the masters. The lower the master number, the higher its priority. The block also has a  busy  signal. Arbitration of the bus is done only while it is inactive. If the bus has already been granted to an agent, even if a bigger priority master requests the bus, the current transaction must complete before the arbiter grants the bus to another master. Continue reading…